Unified systolic array architecture for finite field multiplication and inversion

Ibrahim, Atef; Al-Somani, Turki F.; Gebali, Fayez

doi:10.1016/j.compeleceng.2017.06.014

Cited by 21 publications

(16 citation statements)

References 13 publications

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“…Circles in DG represent the operations performed by the recursive Eqs. (15), (24), (25), (26), (27), (30), and (31). Fig.…”

Section: Proposed Bit-serial Semi-systolic Arraymentioning

confidence: 99%

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Novel bit-serial semi-systolic array structure for simultaneously computing field multiplication and squaring

Ibrahim

2019

IEICE Electron. Express

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This paper presents a novel bit-serial semi-systolic array structure to simultaneously execute modular multiplication and squaring operations in GF(2 m). The architecture is explored by using a systematic methodology based on the proper choice of the scheduling and projection vectors applied to the algorithm dependency graph. The explored architecture has the advantage of sharing the data-path between the two operations, and hence it leads to saving more space compared to the case of using a separate data-path for each operation. Also, the simultaneous calculation of both operations significantly decreases the execution time required to perform modular exponentiation operation, as it mainly depends on these two core operations. Complexity analysis indicates that the developed bit-serial semi-systolic array structure outperforms the latest exiting competitor bitserial systolic and non-systolic structures in terms of area-time (AT) by at least 24%. This makes the proposed structure more appropriate for use in resource-constrained cryptographic processors.

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“…Circles in DG represent the operations performed by the recursive Eqs. (15), (24), (25), (26), (27), (30), and (31). Fig.…”

Section: Proposed Bit-serial Semi-systolic Arraymentioning

confidence: 99%

“…(15), (24), (25), (26), (27), respectively. The lower section represents the last row of the DG and it computes the coefficients of P and S based on equations (30) and (31), respectively. The initial bits…”

Section: Proposed Bit-serial Semi-systolic Arraymentioning

confidence: 99%

Novel bit-serial semi-systolic array structure for simultaneously computing field multiplication and squaring

Ibrahim

2019

IEICE Electron. Express

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“…2) allocating a time value to each node in the DG using a specific timing or scheduling function. 3) mapping several nodes of the DG to a processing element (PE) to form the systolic/semi-systolic array [20,25,26,27,28,29,30]. The DG of the unified multiplication and squaring algorithm over GFð2 m Þ can be extracted from the recursive Eqs.…”

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

“…The DG of the unified multiplication and squaring algorithm over GFð2 m Þ can be extracted from the recursive Eqs. 15, (24), (25), (26), (27), (30), and (31). The extracted DG based on these equations is shown in Fig.…”

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

“…The lower part consists of the last row of the DG (row with the brown nodes) and it computes the coefficients of P and S according to Eqs. (30), and (31), respectively. In the upper part of the DG, the calculated intermediate results of The outputs resulted from the upper part of the DG h l j , g k j , v l j , u k j beside the broadcasted bits of f j are fed as input to the lower part (the last row), as shown in Fig.…”

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

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Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i><sup>m</sup></i>)

Ibrahim

Tariq

Ahmad

et al. 2019

IEICE Electron. Express

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In this paper, we develop an efficient parallel semi-systolic array structure to concurrently compute multiplication and squaring operations in the binary extension field, GF(2 m), for efficient modular exponentiations. The proposed array is well suited to VLSI implementation that it has a regular structure as well as local communications between its processing elements. The obtained results show that the proposed array structure achieves a significant reduction in area-time (AT) complexity by at least 95.9% over the corresponding existing structures.

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Word-serial unified and scalable semi-systolic processor for field multiplication and squaring

Ibrahim

2021

Alexandria Engineering Journal

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Unified systolic array architecture for finite field multiplication and inversion

Cited by 21 publications

References 13 publications

Novel bit-serial semi-systolic array structure for simultaneously computing field multiplication and squaring

Novel bit-serial semi-systolic array structure for simultaneously computing field multiplication and squaring

Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i><sup>m</sup></i>)

Word-serial unified and scalable semi-systolic processor for field multiplication and squaring

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