Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process

Abstract

With the need for fast and low-power radiation-hardened processors, advanced technology process is applied to obtain both high performance as well as high reliability. However, scaling down of the size of the transistor makes the transistor sensitive to outside disturbances, such as soft error introduced by the strikes of the cosmic neutron beams. Besides aerospace applications, such reliability should also be taken into consideration for the sub-100[Formula: see text]nm CMOS designs to ensure the robustness of the circuit. In such circumstances, several radiation-hardened flip-flops are designed and simulated under SMIC 40[Formula: see text]nm process. Simulation results show that with five aspects (performance, power, area, PVT variation and reliability) taken into consideration, TSPC-based DICE and TMR combined architecture has the best soft-error robustness in comparison with other radiation-hardened flip-flops, and the critical charge of such architecture is 490[Formula: see text]fC, which is 12.5X higher than the traditional unhardened flip-flop.

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

“…Note that, in Fig. 1 [13][14][15][16][17][18][19]23], and so on. Similarly, to achieve high reliability, many hardened FFs protected against DNUs have been proposed.…”

“…To mitigate SNUs and DNUs, radiation hardening by design (RHBD) is a widely employed approach. Using RHBD, many novel storage elements, such as latches [5][6][7][8], static random access memories (SRAMs) [9][10][11][12], and flip-flops (FFs) [13][14][15][16][17][18][19]23] have been proposed. Among them, dual-interlocked storage-cells (DICEs) are widely used [20].…”

“…Similarly, to achieve high reliability, many hardened FFs protected against DNUs have been proposed. Typical DNU-hardened FFs include the designs in [16][17][18][19], and so on. However, these FFs still suffer from the following problems.…”

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

“…To mitigate SNUs or even DNUs, many designs of SRAM cells [4,[6][7][8][9][10][11][12][13][14][15] have been proposed by using the Radiation Hardening By Design (RHBD) approach. RHBD, which is also used for designing latches [16][17] and flip-flops [18][19][20], can effectively mitigate the impact of radiation particles on SRAM cells. The traditional SRAM cell is called 6T since it consists of 6 transistors including 2 PMOS and 2 NMOS transistors for value-retention and 2 NMOS transistors for access operations.…”

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

“…On the other hand, the particle may directly strike an OFF-state transistor in a storage element, causing a single-node upset (SNU). Moreover, with the aggressive CMOS technology scaling, circuit integration is becoming much higher and node To mitigate SNUs or even DNUs, using radiation hardening by design (RHBD) techniques, many novel designs of latches [5][6][7] and flip-flops [8][9][10] are proposed, while the other designs mainly consider hardening for static random access memory (SRAM) cells [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. This paper mainly considers hardening for SRAMs.…”