Design and comparison of CMOS Current Mode Logic latches

Usama, Muhammad; Kwaśniewski, T.

doi:10.1109/iscas.2004.1329013

Cited by 15 publications

(10 citation statements)

References 4 publications

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“…MCML is completely differential logic i.e. all signals with their compliments is required [3]. Depending on the logic implemented by PDN, the current is steered through one of the two branches, providing complimentary output signals.…”

Section: MCML Circuitsmentioning

confidence: 99%

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Low power D-latch design using MCML tri-state buffers

Radhika

Pandey

Gupta

et al. 2014

2014 International Conference on Signal Processing and Integrated Networks (SPIN)

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This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed Dlatch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters. The power consumption of the proposed D-latch is compared with the Dlatch designed using switched based MCML tri-state buffers which indicate that the proposed low power D-latch is power efficient. The simulation result also proves that the low power Dlatch consumes 50% less efficient than the other D-latch.

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Section: MCML Circuitsmentioning

confidence: 99%

“…D-latch is the basic circuit used for implementing many fundamental blocks whose performance strongly depends on the D-latch gate performance. D-latch acts as an integral part of various practical applications such as pre-scalars, frequency dividers, and sequential logic circuits [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Low power D-latch design using MCML tri-state buffers

Radhika

Pandey

Gupta

et al. 2014

2014 International Conference on Signal Processing and Integrated Networks (SPIN)

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“…The timing parameters for the Verilog-A based behavioral DR circuit have been derived from a 0.18-m CMOS design [5] (Rise time = fall time = 100 ps, and T cq delay = 75 ps for all flipflops, gate delays = 50 ps). The purpose is to determine the required specifications for the 0.18-m (or 90-nm) library gates operating at 2.5 Gb/s (or higher) that would satisfy a particular jitter tolerance standard.…”

Section: Cmentioning

confidence: 99%

Behavioral test benches for digital clock and data recovery circuits using verilog-A

Ahmed

Orthner²,

Kwaśniewski³

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

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-This paper presents the behavioral implementation of jitter tolerance test benches for digital clock and data recovery circuits using Verilog-A. First, we encode a variable-length Pseudo-Random Bit Sequence (PRBS) generator. Such circuits are widely used to generate test data for a variety of circuits and systems. Using this PRBS generator, we set up a test bench for the evaluation of jitter tolerance. A novel simulation methodology is described that modulates the amplitude and frequency of the jitter sinusoid iteratively to find the jitter tolerance. We conclude with a comparison of jitter tolerance simulation results, computed using various PRBS lengths, for the data recovery circuit under test.

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“…2 [2]. The current switching between the pairs takes place by the complementary signals of the clock.…”

Section: Latchesmentioning

confidence: 99%