Metastability analysis of CMOS current mode logic latches

Usama, Muhammad; Kwaśniewski, T.

doi:10.1109/ccece.2005.1557269

Canadian Conference on Electrical and Computer Engineering, 2005.

DOI: 10.1109/ccece.2005.1557269

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Metastability analysis of CMOS current mode logic latches

Muhammad Usama

T. Kwaśniewski

Abstract: Abstract

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“…Flip flop in metastable state and the x-axis denotes the time taken by the flip flop output to settle after entering into metastable state[2][3][4] …”

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confidence: 99%

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Linearity Improvement in Vernier Delay Chain Based Time Difference Amplifiers

Ramesh¹

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Time difference amplifiers are used in fluorescence experiments where the input time differences are in picoseconds. The key challenge is to provide the linearity of such amplifiers with sufficient gain over the required input range. This amplifier has a gain greater than 2 ps ps , with the input ranging from 10 pS to 1000 pS. The gain error is found to be less than 10% at a temperature of 25 • C , voltage range of 800mV to 1.2 V. The overall power consumption from simulation is 4 mW. This design uses differential signalling based architecture and is an open loop system to realize these specifications. Initially results of the design were verified using simulation techniques and then the physical implementation was done resulting in an integrated circuit that was fabricated and tested. While the open loop approach in this implementation will make it unable to correct the gain with temperature variations, the circuit has features that can integrate well with a feedback system to convert it to a closed loop system.

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“…Flip flop in metastable state and the x-axis denotes the time taken by the flip flop output to settle after entering into metastable state[2][3][4] …”

mentioning

confidence: 99%

“…The pour is connected to the ground plane. PCB floor plan, pre routing and post routed images of the PCB are shown inFigure 5.3 and 5 4…”

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confidence: 99%

Linearity Improvement in Vernier Delay Chain Based Time Difference Amplifiers

Ramesh¹

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Metastability analysis of CMOS current mode logic latches

Abstract: Abstract

Cited by 1 publication

References 2 publications

Linearity Improvement in Vernier Delay Chain Based Time Difference Amplifiers

Linearity Improvement in Vernier Delay Chain Based Time Difference Amplifiers

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