Design and analysis of high speed shift register using Single clock pulse method

Rajaram, Anand; Premalatha, P.; Sowmiya, R.; Saravanan, S.; Vijaysai, R.

doi:10.1109/iccci.2013.6466252

Cited by 14 publications

(4 citation statements)

References 3 publications

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“…Also, the delay report has been presented. Thus, we can show that our proposed design has achieved the delay of the 4.394 ns as compared to the 6ns in the previous design [23].…”

Section: Discussionmentioning

confidence: 65%

“…We have presented the design of the scan D-Flip Flops and various Shift registers have been designed to compare the time delay with the conventional design. Thus 26.7% reduction in the delay is reported as compared to previous design [23].…”

Section: Introductionmentioning

confidence: 70%

“…In figure 20, we have shown the final delay of the proposed design. The total delay is shown to be 4.394ns as compared to the conventional design of the shift register [23] was reported to be 6ns. Thus 26.7% reduction in the delay has been reported here.…”

Section: B With Out Hold Mode Flip Flopmentioning

confidence: 91%

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Design And Implementation of High Speed Scan-Hold Flip Flop based Shift Registers

2017

IJAERD

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There has been a great increase in the number of electronic devices and the requirement of high speed design has been increasing exponentially. Here, thus the design of the flip-flop and the sequential logic devices has been a prime constraint in the overall speed performances. Thus to increase the overall speed performance of the flip-flip design, various methodologies have been proposed. The major shift registers used in various digital devices are Serial-In -Serial-Out, Universal shift registers has been developed. In our proposed work, we have proposed scan mode Flip-Flop and these flip-flop based Shift register design. The proposed modified design of the scan multiplexer based D Flip-Flip has been used for the implementation of various shift registers. Here, the Serial In Serial Out, Parallel In Parallel out, and Universal Shift Register design has been presented. Our proposed design is shown to have lower delay and minimize the gate count. The simulation has been done using Xilinx ISE 9.1 and Target device is to be SPARTAN 3E.

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“…Also, the delay report has been presented. Thus, we can show that our proposed design has achieved the delay of the 4.394 ns as compared to the 6ns in the previous design [23].…”

Section: Discussionmentioning

confidence: 65%

Section: Introductionmentioning

confidence: 70%

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Design And Implementation of High Speed Scan-Hold Flip Flop based Shift Registers

2017

IJAERD

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“…As vary the environmental Temperature of device the power varies because the resistance and mobility of electron and holes are also varying [13,14] (Graph 38.4). …”

Section: Temperature V/s Power Curvementioning

confidence: 99%

Design of Low Power Shift Register in Nano Scale Domain Using FinFET

Gupta

Akashe

2015

Springer Proceedings in Physics

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In this paper, we have calculated and described the Shift Register Design using FinFET. Shift Register is used as to shift the value of any register, in microprocessor, microcontroller and shifted value is also equal to multiplication of any binary no. by 2. According to Moore's law the no. of transistor in a scrupulous chip area is doubled in every 18 months. This proclamation gives new epoch of VLSI meadow. If we want to increase the no. of component in chip area so we reduce the size of component. Applying this attribute in chip component, the size of transistor reduced. As we scale down the device parameter after a certain rule, the short channel effects like leakage power, surface scattering, velocity saturations, takes place. Fin-FET is a superior device to eradicate or decrease above mentioned problems. We analyze the various parameters like temperature effect to the total power, total power consumption, average DC power, calculation etc. For calculation these results we are using cadence tools. After simulating the circuit we get values of Average DC power is 777.6 nW, Average Transient Power Consumption is 67.20 nW, Delay is 20 nS.

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FPGA implementation of automatic seizure detection in EEG signals using machine learning algorithm

Sajja,

Rooban

2024

Discov Appl Sci

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Design and analysis of high speed shift register using Single clock pulse method

Cited by 14 publications

References 3 publications

Design And Implementation of High Speed Scan-Hold Flip Flop based Shift Registers

Design And Implementation of High Speed Scan-Hold Flip Flop based Shift Registers

Design of Low Power Shift Register in Nano Scale Domain Using FinFET

FPGA implementation of automatic seizure detection in EEG signals using machine learning algorithm

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