Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network

Lee, Jun-Ho; Kyung, Kimyung; You, Minyoung; Lee, Hyungdong; Park, Kunwoo; Chung, Byong-Tae

doi:10.1109/epep.2007.4387131

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…For worst-case noise behavior we model the IDD07 condition [9], all banks interleaved read current, which is widely acknowledged as the condition generating the most power-supply noise. For static IR-drop calculations we use an average system power value generated from Micron's system design power calculation spread-sheet.…”

Section: Power Mapsmentioning

confidence: 99%

Power delivery system architecture for many-tier 3D systems

Healy

Lim

2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Many-tier systems are the future of 3D integration. In this work we explore power delivery system design for these large scale devices. We have developed a scalable many-tier design that contains one tier of processors and eight tiers of DRAM. These nine tiers comprise a 'set' that can be stacked any number of times. Previously, we have examined the dynamic and static power noise scaling behavior of various components of this system. Now, we present studies on two key aspects of power system architecture in these systems and their impact on power supply noise. First, we examine the addition of a dynamic noise-limiting turn-on policy and show that it can reduce dynamic power supply noise by 37% with almost no impact on system performance. Next, we present interesting results comparing different power/ground TSV topologies and show that a spread TSV distribution can lower both DC and dynamic power supply noise in the case that the many-tier stack contains low power tiers, such as memory tiers. We also show that ignoring TSV inductance when calculating dynamic noise can result in a 14.8% underestimate. IntroductionPerformance scaling in microprocessors has reached a major barrier because of the disparity between wire and transistor size scaling. 3D integration has emerged as a potential solution to this problem. However, there are many unresolved design issues related to 3D integration. In this work we explore power distribution network design for largescale 3D systems and present two techniques that reduce power supply noise for these large-scale systems.The largest factor creating transient noise is the so-called "first droop" noise that results from the interaction between inductance in the package and the on-and off-chip decoupling capacitance (decap) during sleep transitions. Modern microprocessors experience frequent power gating and sleep transition events as a result of aggressive power reduction techniques. These power gating events cause large transient changes in the current demand in the power supply network. For 3D systems the through silicon vias (TSVs) add inductance to that already in the package, exacerbating the power noise problem. In this work we use "dynamic noise" to refer to the first droop noise caused by power gating events and "IR-drop" to refer to the voltage drop in the power network during normal operation.Thermal impacts are another major factor that must be considered when designing 3D systems. Air-cooled heatsinks will be unable to cope with the power density of large-scale 3D systems. Recent work has focused on implementing micro-fluidic channels [1] onto the backs of 3D stacked ICs to remove heat using liquid-phase fluids. The heat removal capacity of these systems is very promising. In this work we

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Section: Power Mapsmentioning

confidence: 99%

Power delivery system architecture for many-tier 3D systems

Healy

Lim

2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

show abstract

“…For worst-case noise behaviour we model the IDD07 condition [13], all banks interleaved read current, which is widely acknowledged as the condition generating the most power-supply noise. For static IR-drop calculations we use an average system power value generated from Micron's system design power calculation spread-sheet.…”

Section: A Power Mapsmentioning

confidence: 99%

A study of stacking limit and scaling in 3D ICs: an interconnect perspective

Healy

Lim

2009

2009 59th Electronic Components and Technology Conference

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An examination of large-scale stacking of 3D integrated ICs from a power-supply and thermal reliability perspective is presented. Noise characteristics and scaling issues related to through-silicon-via (TSV) size and pitch as well as other power-supply topology characteristics are included. Thermal simulations are carried out assuming the use of micro-fluidic heatsinks to provide cooling to systems with power dissipation of up to 525 watts and 46 integrated silicon tiers. Results indicate that these large systems are feasible given sufficient planning. Power-delivery-bump pitch is identified as the most important factor influencing IR-drop and dynamic noise. Contact resistance also may become a major limiting factor. I. IntroductionThe shift to the multi-core era has increased demand on the memory bandwidth of high performance processor systems. 3D integration of memory and processors has emerged as a potential solution to the memory bandwidth problem. However, there are several unanswered questions regarding 3D integration. In this work we study integration scaling from a power-supply and thermal perspective. As the number of tiers in a 3D system increase, the uppermost tiers become separated from the power supply bumps by increasing resistance and inductance. The cause of these parasitics is the through-silicon vias (TSVs) that provide communication between tiers. Additionally, increasing integration quickly raises the volumetric power density of the IC stack.The largest factor creating transient noise is the so-called "first droop" noise that results from the interaction of the inductance in the package and the on-chip decap during sleep transitions. Power gating due to sleep transitions causes large transient changes in the current demand in the power supply network. In the case of 3D systems the TSVs add inductance of their own to that which naturally exists in the package.Thermal impacts are a major factor that must be considered when designing 3D systems. For the purpose of maximum 3D integration studies standard air-cooled heatsinks will be unable to cope with the power density of these systems. Recent work has focused on implementing micro-fluidic channels [1] onto the backs of 3D stacked ICs for the purpose of removing heat using liquid-phase fluids. The heat removal capacity of these systems is very promising. In this work we assume that microfluidic heatsinks are used to dissipate heat, and design our power distribution model around this assumption.

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Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network

Cited by 2 publications

References 3 publications

Power delivery system architecture for many-tier 3D systems

Power delivery system architecture for many-tier 3D systems

A study of stacking limit and scaling in 3D ICs: an interconnect perspective

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