Depletion/enhancement CMOS for a lower power family of three-valued logic circuits

Heung, A.; Mouftah, H.T.

doi:10.1109/jssc.1985.1052354

Cited by 114 publications

(42 citation statements)

References 9 publications

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“…Ternary NOR gate is three valued NOR gate which is an improved version of binary NOR gate. The outputs of a ternary NOR gate can be determined using this equation [15], [16]:…”

Section: Ternary Nor Gatementioning

confidence: 99%

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Analytical Distinction Between Cntfet Based And Mosfet Based Srams And Logic Gates

Nandy¹,

Dutta²,

Mahmood³

2015

ELELIJ

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In this review, we compare the distinct properties of Carbon Nanotube Field Effect Transistor (CNTFET) based applications with MOSFET based applications in memory and digital electronics technology. In nanoelectronics circuitry, CNTFET has opened new dimensions with extreme opportunities of improvement in circuit performance due to its extreme mobility, ballistic conduction and so forth. Apart from being an excellent conductor, CNTFET can also be used as a memory unit for its good stability in storing a data bit and as digital circuits (multi-valued logic gates) for its better PDP and sensitivity. This paper discusses the design and read-write mechanisms of 6T and 8T CNTFET SRAM cell and a comparative study among themselves based on their corresponding advantages and disadvantages. Moreover, superiority of CNTFET SRAM over MOSFET SRAM is analyzed in terms of

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“…Ternary NOR gate is three valued NOR gate which is an improved version of binary NOR gate. The outputs of a ternary NOR gate can be determined using this equation [15], [16]:…”

Section: Ternary Nor Gatementioning

confidence: 99%

“…Ternary NAND gate is a better version which can be operated by three types of input. The function of two entry ternary NAND gate is defined by the following equation [15], [16]:…”

Section: Ternary Nand Gatementioning

confidence: 99%

Analytical Distinction Between Cntfet Based And Mosfet Based Srams And Logic Gates

Nandy¹,

Dutta²,

Mahmood³

2015

ELELIJ

View full text Add to dashboard Cite

show abstract

“…Furthermore, serial and serial-parallel arithmetic operations can be carried out faster if the ternary logic is employed. Extensive research on design and implementation of ternary logic using CMOS can be found in the technical literature [19,20]. Chip area and power dissipation can be reduced by more than 50% using an efficient MVL implementation for a signed 32-bits multiplier compared to its fastest binary counterpart [11].…”

Section: Ternary Logic Gate Design Using Cntfetmentioning

confidence: 99%

“…The functions of the two-entry ternary NAND and NOR gates are defined by the following two equations, respectively [20]:…”

Section: Ternary Nor and Nand Gatesmentioning

confidence: 99%

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Kim¹

2011

Transactions on Electrical and Electronic Materials

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As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

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“…An interesting ternary full adder implemented in Depletion/Enhancement CMOS technology was presented in 1985 [9], but it didn't achieved any commercial success.…”

Section: The Balanced Ternary Numbering Systemmentioning

confidence: 99%

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Gundersen

Berg

2007

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

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Depletion/enhancement CMOS for a lower power family of three-valued logic circuits

Cited by 114 publications

References 9 publications

Analytical Distinction Between Cntfet Based And Mosfet Based Srams And Logic Gates

Analytical Distinction Between Cntfet Based And Mosfet Based Srams And Logic Gates

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

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