Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

MOS Characteristics of Substituted Al Gate on High-<tex>$kappa$</tex>Dielectric

“…No polysilicon depletion is also confirmed from the C-V curve measured on SA gate nMOSFET (data not shown here), indicating full substitution of n polysilicon with Al. As reported, that FUSI process shows EOT reduction compared to n polysilicon gate [8], the EOT reduction phenomenon is also observed in SA process and the amount of EOT reduction is identical for both processes. However, the EOT reduction amount shows dielectric dependence.…”

“…However, the achievement of such work functions on a high-dielectric is still a challenge because of Fermi-level pinning and thermal instability of the interface as well as the metal film itself, especially for the metals with low work function [2]- [5]. Recently, fully silicided (FUSI) metal gates are reported to have better thermal stability [6]- [8]. However, it is still not easy to achieve a work function low enough for bulk nMOSFET using FUSI metal gate on high-dielectric.…”

45nm LSTP FET with FUSI Gate on PVD-HfO2 with excellent drivability by advanced PDA treatment

“…After the S/D silicidations, Ni-FUSI was carried out [2]. Fig.1 shows the TEM cross-section of the Ni-FUSI transistor with gate lengths of around 55nm.…”

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

“…pMOSFET-FUSI transistors were fabricated following the flow described in [11]. As a gate dielectric SiON using a decoupled plasma nitridation (DPN) or a metal-organic chemicalvapor deposition (MOCVD) HfSiON with different Hf contents (Hf/Hf+Si equals 23%, 53%, or 65%) with an 800 • C NH 3 postdeposition anneal, was used.…”

“…(S/D) and the poly-Si gate were performed independently using a chemical-mechanical polishing (CMP) approach [11] [ Fig. 1(b)].…”