Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

Lee, Y. J.; Jan, G.; Wang, Y. J.; Pi, K.; Zhong, Tom; Tong, Ru-Ying; Lam, Vinh; Teng, Jeffrey W.; Huang, Ko-Fan; He, Renren; Le, S.; Torng, Terry; DeBrosse, J.; Maffitt, T.; Long, Christopher; Gallagher, W. J.; Wang, P. K.

doi:10.1109/vlsi-tsa.2013.6545595

Cited by 7 publications

(4 citation statements)

References 6 publications

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“…Later on, most of semiconductor companies across the globe recruited their own STT-MRAM teams focusing on STT-MRAM R&D. The momentum in pursuit of STT-MRAM technology as a future memory is greater than ever before. With a number of test chips demonstrated in the past decade [92,109,110,[165][166][167][168](see Figure 3.24), STT-MRAM R&D reached a peak in 2019. In this year, Everspin launched a game-changing 1 Gb standalone STT-MRAM product with DDR4 interface, targeting the replacement of DRAM in some applications such as enterprise SSDs [28].…”

Section: Mram Commercializationmentioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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Section: Mram Commercializationmentioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…Spin transfer torque magnetic random access memory (STT-MRAM) using magnetic tunnel junction (MTJ) is attracting a great deal of attention because of its potential for nonvolatile, high-speed, and high-density memory. [1][2][3][4][5][6][7][8][9] In order to achieve an STT-MRAM with a large capacity comparable to dynamic random access memories (DRAMs), it is obviously desirable to adopt a 1-transistor and 1-MTJ (1T-1MTJ) memory cell because of its simple structure. But early STT-MRAMs [1][2][3][4] used to adopt 2-transistor and 1-MTJ (2T-1MTJ) cell, because the current drivability of the memory cell transistor was insufficient for the required large switching current of MTJs.…”

Section: Introductionmentioning

confidence: 99%

“…[10][11][12][13][14][15][16][17][18] Thus 1T-1MTJ STT-MRAMs with several ten nm MTJs integrated on 40-90 nm CMOS circuits have been realized. [5][6][7][8][9] However, there still exists room for more improvement of the STT-MRAM's operational margin and memory cell size from a viewpoint of the asymmetric switching current of the MTJ. Figure 1 illustrates typical structure and resistancecurrent (R-I) characteristics of an MTJ.…”

Section: Introductionmentioning

confidence: 99%

Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

Koike

Ohsawa

Honjo

et al. 2014

Jpn. J. Appl. Phys.

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This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the T and the MTJ, either PMOS — bottom pin structure or NMOS — top pin structure can be a promising choice. Focusing on the PMOS–bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure’s effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90 nm CMOS/100 nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6 V. It will be an effective solution for 1T–1MTJ memories.

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“…Fe-RAM 21 of these MTJs is not as advanced as in-plane MTJs. In [26], the authors use a PMA MTJ structure to study write ability of STT-RAM in an array setup. The authors also raise the SL voltage above V SS during a write "0" operation and provide a WL voltage greater than V DD to ensure correct operation.…”

Section: Challenges and Available Solutionsmentioning

confidence: 99%

Improving Reliability and Power Consumption of Memories in Battery-less Systems-on-Chip

Yahya¹

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Recent projections by Cisco have suggested that more than 50 billion devices are expected to sense, process and transmit information as part of the internet of things (IoT) by 2020. These devices will target a wide range of applications including but not limited to health monitoring, environmental monitoring, infrastructure monitoring, smart homes, and smart cars. Due to the varying environmental conditions under which these devices are expected to operate and to their large number, battery replacement has become a major concern. Recently, ultra-low power (ULP) systems-on-chip (SoCs) that can operate solely on harvested energy have been presented. A number of challenges face the dispersion of this technology: 1) reducing the power and energy consumption of the building blocks of these SoCs to stay within the budget of the energy harvester, 2) operating reliably under varying harvesting conditions, and 3) maintaining critical data in the event of a power loss. This work will investigate techniques to address these challenges and enable battery-less operation. One of the main techniques used to reduce power consumption is scaling the supply voltage (V DD) below the threshold voltage of the transistors (sub-threshold operation). Due to the quadratic dependence of power on V DD , Reducing V DD to the sub-threshold domain will result in significant power savings thus enabling battery-less operation. However, with supply scaling comes the additional challenges of reduced reliability and performance. While performance is an acceptable trade-off in applications with low throughput requirements, ensuring reliability at low voltages remains a challenge. As V DD is scaled to the sub-threshold region, the onto off current ratio of a transistor is reduced, and the impact of process i find a chapter in my dissertation or a section in my paper without errors and with flawless English, you'll directly know that Haya went over it. Fadi's advice on life in the US taught me a lot and made my transition so much easier. Finally, I owe all my successes in life to my personal hero: my dad. He has been a constant example of what success, modesty, kindness, intelligence, and integrity are like. My love of learning is something I have inherited from him. No words can express my love.

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Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array

Cited by 7 publications

References 6 publications

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

Improving Reliability and Power Consumption of Memories in Battery-less Systems-on-Chip

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