Delay Optimized Novel Architecture of FIR Filter using Clustered-Retimed MAC unit Cell for DSP Applications

Subathradevi, S.; Vennila, C.

doi:10.18576/amis/110427

Cited by 4 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Its basic structure is shown in Fig. 4 FIR filter of linear phase [11] kind could save the resources having to the coherent or symmetrical attributions of impulse response coefficients. Consequently, the primal theme of FIR filter designing was the computation of k-times convolution, which directs to a considerable measure of multiplications over the implementation of hardware.…”

Section: Fir Filter Designmentioning

confidence: 99%

See 1 more Smart Citation

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

Yadav

Prakash²,

Saraswathi³

2022

EJENG

View full text Add to dashboard Cite

The primary motive of this paper is to give the design and implementation of RNS (Residue Number System) based Area efficient and excessive-overall performance FIR filter of 4-tap, eight-tap, 16-tap of input eight bit. Additionally, RNS mathematics is a treasured device for theoretical research of the limits of fast mathematics. These proposed strategies additionally have a few additions operation, through the use of convention adder will decrease the speed of operation and additionally increase the number of logic gates. So, to conquer the one's issues we are using Ladner Fischer parallel prefix adder to lower the delay and area. First, the multiplier is designed through the use of RNS approach. In which the delay is decreased through 78.57% and power dissipation is likewise reduced to 64.65% for the RNS_PPA multiplier. A combination of those algorithms generates a brand-new structure of excessive speed and low implementation area in a single multiplier for FIR filter using Xilinx 14.7.

show abstract

Section: Fir Filter Designmentioning

confidence: 99%

“…𝑃𝑠[𝑖: 𝑘] (10)3) Post-Processing StageGenerally in the third stage of the Ladner Fischer adder ,the output sum is the XOR operation of the inputs signals and the carry generated by the preceding bit in the second stage of the operation[20]. The final output sum can be represented by Boolean equation(11).…”

mentioning

confidence: 99%

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

Yadav

Prakash²,

Saraswathi³

2022

EJENG

View full text Add to dashboard Cite

show abstract

Efficient Filter Implementation Using Cutset Retiming and Pipelining Approaches

Nirmal

Mariammal

2021

Advances in Automation, Signal Processing, Instrumentation, and Control

View full text Add to dashboard Cite

An Efficient FIR Filter Based on Hardware Sharing Architecture Using CSD Coefficient Grouping for Wireless Application

SRIVAST

Raj

2021

Wireless Pers Commun

View full text Add to dashboard Cite

FIR lter is an essential part of digital signal processing that is extensively used in many areas such as wireless application and digital processing system. An e cient recursive lter is always required for realtime applications such as 5G network, smart robots and Internet of Things etc. The design of FIR lter is inherently stable and has a linear phase characteristic but its implementation often involves complexity and a large lter length to achieve speci c design requirements. In this paper, the complexity of FIR lter is reduced by eliminating the repeated subexpression in a canonic sign digit(CSD)number system based lter operation. A new grouping method has been proposed for the CSD number system-based lter coe cient to minimize the number of unpaired nonzero bits in the lter coe cient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11% as compared to other existing schemes. Further, an e cient FIR lter with hardware sharing architecture is designed and implemented to achieve a 14.65% reduction in average power consumption and the average operation speed is increased by 10.1% in comparison to the other existing lter structures.

show abstract

Delay Optimized Novel Architecture of FIR Filter using Clustered-Retimed MAC unit Cell for DSP Applications

Cited by 4 publications

References 5 publications

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

Efficient Filter Implementation Using Cutset Retiming and Pipelining Approaches

An Efficient FIR Filter Based on Hardware Sharing Architecture Using CSD Coefficient Grouping for Wireless Application

Contact Info

Product

Resources

About