Delay-optimized floating point fused add-subtract unit

et al. 2016

Self Cite

This paper presents a floating point fused dot-product (FDP) unit with latency reduced. The proposed FDP unit performs the dot-product operation of four floating point numbers: ab ² cd and is implemented with dual-path algorithm. The proposed FDP is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that our proposed FDP unit is 24∼30% faster and 36.4% less area than the fastest FDP in previous work. We also use the proposed FDP unit and our previously designed FAS (fused add-subtract) unit to implement a FFT Radix-2 Butterfly (R2BF) unit. The latency of our proposed R2BF unit is improved roughly by 34% and the area is reduced by 41.6%, compared to the fastest 2's-complement butterfly unit.

Section: Results and Comparisonsmentioning

confidence: 99%

“…The total delay of the shifters ">>1" and multiplexers M2(M3) is 1L. The details of the mechanism is explained in our previously proposed FAS [2].…”

Section: Implementation and Techniquesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A two-item floating point fused dot-product unit with latency reduced

et al. 2016

Self Cite

“…In order to scientifically compare the speed of a variety of different computing units employed, we use logic level [2,11] to estimate the latency of different circuits without limitation of manufacturing technology. Generally speaking, we assumed the XOR gate involves 2 logic levels of delay which is two times that of the AND/OR gate.…”

Section: Introductionmentioning

confidence: 99%

Delay-optimized realization of 2-parallel delayed LMS adaptive FIR filter

et al. 2017

Self Cite

Motivated by improvement of convergence characteristics and throughput, this work develops a delay-optimized VLSI realization of the adaptive filter based on the 2-parallel delayed LMS (PDLMS) algorithm. The proposed design uses a novel parallel FIR filter structure based on the fast FIR algorithm. The throughput of the proposed architecture is not only two times that of the traditional structure at the same frequency, but also the convergence characteristic is close to that of the LMS algorithm. The finegrained dot-product unit, fine-grained fused multiply-add unit and multipleinput-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 25% less power and nearly 24% less area-delay-product (ADP) than the best existing structure.

VLSI implementation of the modified sign-error LMS adaptive algorithm

et al. 2017

Self Cite

Motivated by reduction of computational complexity, this work develops a delay-optimized VLSI architecture of the adaptive filter based on the modified sign-error LMS (MSLMS) algorithm. The proposed algorithm uses a three-level quantization strategy applied to the modified sign function containing a threshold parameter. The amount of computation of the proposed architecture is not only less than half of the traditional structure, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed design for filter length 8-tap has roughly 31% less power and 53% less area-delay-product (ADP) than the best of existing structures.