VLSI implementation of the modified sign-error LMS adaptive algorithm

Abstract

Motivated by reduction of computational complexity, this work develops a delay-optimized VLSI architecture of the adaptive filter based on the modified sign-error LMS (MSLMS) algorithm. The proposed algorithm uses a three-level quantization strategy applied to the modified sign function containing a threshold parameter. The amount of computation of the proposed architecture is not only less than half of the traditional structure, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed design for filter length 8-tap has roughly 31% less power and 53% less area-delay-product (ADP) than the best of existing structures.