Abstract:This paper presents a floating point fused dot-product (FDP) unit with latency reduced. The proposed FDP unit performs the dot-product operation of four floating point numbers: ab ² cd and is implemented with dual-path algorithm. The proposed FDP is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that our proposed FDP unit is 24∼30% faster and 36.4% less area than the fastest FDP in previous work. We also use the proposed FDP unit and our previously designed F… Show more
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