Delay optimization using SOP balancing

Mishchenko,; Jang,; Kravets,

doi:10.1109/iccad.2011.6105357

Cited by 28 publications

(17 citation statements)

References 17 publications

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“…Previous work on AIG level minimization [21] has shown that the reduction in AIG levels correlates well with the reduction of delay after technology mapping for both standard cells and LUT-based FPGAs.…”

Section: A Case Study Of Lms: Aig Level Mininizationmentioning

confidence: 87%

“…On the application side, a closely related work is that on SOP balancing [21], which has the goal of reducing the AIG level count, as a preprocessing step before technology mapping into standard cells or LUTs. Both types of mapping have been tried in [21] with substantial delay improvements.…”

Section: Previous Workmentioning

confidence: 99%

“…In the same work [21] it was shown that AIG level can be optimized by applying SOP balancing to K-feasible cuts of each node. In this case, SOPs of the cut functions are computed and decomposed using the arrival times of cut leaves in order to minimize the arrival time of the cut root.…”

Section: A Case Study Of Lms: Aig Level Mininizationmentioning

confidence: 99%

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Lazy man's logic synthesis

Yang

Wang

Mishchenko

2012

Proceedings of the International Conference on Computer-Aided Design

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Abstract-Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by logic synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy" approach to logic synthesis based on the following observations: (a) optimal or near-optimal circuits for many practical functions are already derived by the tools, making it unnecessary to implement new algorithms or even run the old ones repeatedly; (b) larger circuits are composed of smaller ones, which are often isomorphic up to a permutation/negation of inputs/outputs. Experiments confirm these observations. Moreover, a case-study shows that logic level minimization using lazy man's synthesis improves delay after LUT mapping into 4-and 6-input LUTs, compared to earlier work on high-effort delay optimization.

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Section: A Case Study Of Lms: Aig Level Mininizationmentioning

confidence: 87%

Section: Previous Workmentioning

confidence: 99%

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Lazy man's logic synthesis

Yang

Wang

Mishchenko

2012

Proceedings of the International Conference on Computer-Aided Design

Self Cite

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“…Since our study targets depth-minimality, we considered depth-oriented synthesis scripts. For AIG-optimization, we used the script resyn2rs; if -g iterated 10 times [22]. For MIG-optimization, we used the synthesis script described in [25].…”

Section: A Methodologymentioning

confidence: 99%

Multi-level logic benchmarks: An exactness study

Amarù

Soeken

Haaswijk

et al. 2017

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nodes. Exact benchmarks are of paramount importance to design automation because they allow engineers to test the efficiency of heuristic techniques used in practice. When dealing with two-level logic circuits, tools to generate exact benchmarks are available, e.g., espresso-exact, and scale up to relatively large size. However, when moving to modern multi-level logic circuits, the problem of deriving exact benchmarks is inherently more complex. Indeed, few solutions are known. In this paper, we present a scalable method to generate exact multi-level benchmarks with the optimum, or provably close to the optimum, number of logic levels. Our technique involves concepts from graph theory and joint support decomposition. Experimental results show an asymptotic exponential gap between state-ofthe-art synthesis techniques and our exact results. Our findings underline the need for strong new research in logic synthesis.

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“…AIG balancing: Balancing is a technique that aims to reduce the number of levels in an AIG [10]. It is done in two main steps.…”

Section: Logic Synthesismentioning

confidence: 99%

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

Shum

Anderson

2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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FPGA CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circuit quality, i.e. noise, that arise when CAD algorithms are altered to choose randomly when faced with such equal-cost alternatives. Noise sources are identified in logic synthesis and technology mapping algorithms, and experimental results are presented which show standard deviations of 3.3% and 3.7% from the mean in post-routed delay and power. As a means of dealing with this variation, early timing and power prediction metrics can be applied after technology mapping to find the best circuits in the presence of noise. When applied to designs with over 1.5% variation in delay and power, the best prediction models have a 40% probability of capturing the best circuit when predicting the top 10% of circuits in a group of noise-injected circuits.

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Delay optimization using SOP balancing

Cited by 28 publications

References 17 publications

Lazy man's logic synthesis

Lazy man's logic synthesis

Multi-level logic benchmarks: An exactness study

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

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