Defect-less trench filling of epitaxial Si growth by H/sub 2/ annealing

Yamauchi, S.; Urakami, Yasushi; Tuji, N.; Yamaguchi, Hitoshi

doi:10.1109/ispsd.2002.1016189

Cited by 5 publications

(2 citation statements)

References 2 publications

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“…For these issues, many process research studies and developments such as anisotropic epitaxial growth have been performed. [17][18][19] Consequently, SJ-MOSFETs using the trench filling method have attained a R ON 0A below the Si limit, [20][21][22][23][24][25][26][27] and the lowest reported R ON 0A of a fabricated SJ-MOSFET was 7.8 m³0cm 2 at a breakdown voltage of 685 V, which was lower than that of the SJ-MOSFET fabricated using the multistep epitaxy method. 24) Since SJ-MOSFETs can reduce the R D 0A markedly, it is also important to minimize the R CH 0A, R ACC 0A, and R JFET 0A.…”

Section: Introductionmentioning

confidence: 99%

Numerical analysis of specific on-resistance for trench gate superjunction MOSFETs

Ōnishi

Hashimoto

2015

Jpn. J. Appl. Phys.

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The numerical analysis results and theoretical limit of specific on-resistance (RON·A) for a parallel trench gate superjunction (SJ) MOSFET where a striped trench gate structure is parallel to a striped SJ structure and a perpendicular trench gate SJ-MOSFET where the striped trench gate structure is perpendicular to the striped SJ structure are presented. Analytical equations for relationships between breakdown voltage and RON·A are verified by device simulation and show good agreement with simulation results. When the MOSFET cell pitch is below half of the SJ pitch, in accordance with the numerical analysis results, the RON·A of the perpendicular SJ-MOSFET is smaller than that of the parallel SJ-MOSFET. This is due to the fact that the drift resistance including a current spreading effect and the channel resistance including a current narrowing effect in the perpendicular SJ-MOSFET are reduced by reducing the MOSFET cell pitch.

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Section: Introductionmentioning

confidence: 99%

Numerical analysis of specific on-resistance for trench gate superjunction MOSFETs

Ōnishi

Hashimoto

2015

Jpn. J. Appl. Phys.

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“…below 200 V. For a column width less than 3 µm, the approach of using multiple-layer epitaxial growth and implantation processes [11] to form vertical p-n columns becomes unsuitable due to the constraints of multiple misalignments of masks, auto-doping in the epitaxial process and thermally induced dopant inter-diffusion in annealing processes. Instead, the silicon trench and selective epitaxial growth processes can be used at a lower temperature to overcome the above-mentioned constraints [21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Practical superjunction MOSFET device performance under given process thermal cycles

Zhong¹,

Liang²,

Samudra³

et al. 2004

Semicond. Sci. Technol.

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The performance of specific on-state resistance (R on,sp ) versus breakdown voltage (V br ) of a superjunction power MOSFET device is constrained by the quality of its sidewall junctions formed by neighbouring p and n columns in the drift region. The p-n junction quality, which is inevitably affected by the inter-column dopant diffusion in practice, will limit the R on,sp -V br device performance if no compensation measure is taken. A detailed study of the influence of sidewall junction quality on performance at various column widths under given thermal process conditions was carried out through process and device simulations. The study discovers the practical optimal performance of superjunction (SJ) DMOS and UMOS structures under the influence of dopant inter-column diffusion. Analysis of the phenomenon shows that the degradation of the breakdown voltage is caused by the p and n column charge imbalance. Practical SJ performance equations, which model the influence reasonably well, are derived in the paper. These equations can be used to predict the practical performance of an SJ device under given thermal conditions, which in turn guides us to the compensation measures required to achieve better performance.

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High-voltage semiconductor devices: status and trends

Dolny

2005

Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2005.

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Defect-less trench filling of epitaxial Si growth by H/sub 2/ annealing

Cited by 5 publications

References 2 publications

Numerical analysis of specific on-resistance for trench gate superjunction MOSFETs

Numerical analysis of specific on-resistance for trench gate superjunction MOSFETs

Practical superjunction MOSFET device performance under given process thermal cycles

High-voltage semiconductor devices: status and trends

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