Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM

Weckx, Pieter; Kaczer, B.; Toledano-Luque, M.; Grasser, T.; Roussel, Ph.; Kükner, Halil; Raghavan, Praveen; Catthoor, Francky; Groeseneken, G.

doi:10.1109/irps.2013.6531974

Cited by 46 publications

(28 citation statements)

References 17 publications

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“…6 (c)]. While this feature might be beneficial for low duty-cycle circuit operation [14], larger shifts are expected at short time scales relevant for high-frequency logic circuits.…”

Section: B Fast Emsm: Pbti Relaxation and Lifetime Extrapolationmentioning

confidence: 99%

Suitability of high-k gate oxides for III–V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Franco

Alian

Kaczer

et al. 2014

2014 IEEE International Reliability Physics Symposium

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We present a comprehensive study of Positive Bias Temperature Instability (PBTI) in In 0.53 Ga 0.47 As devices with Al 2 O 3 gate oxide, and with varying thickness of the channel quantum well. We show significant instability of the device electrical parameters induced by electron trapping into a wide distribution of defects in the high-k layer, with energy levels just above the InGaAs conduction band. A significant PBTI dependence on the channel thickness is found and ascribed to quantization effects. We argue that, in order to be relevant for production, the superior transport properties of III-V channels will need to be demonstrated with more stable high-k gate stacks.

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“…6 (c)]. While this feature might be beneficial for low duty-cycle circuit operation [14], larger shifts are expected at short time scales relevant for high-frequency logic circuits.…”

Section: B Fast Emsm: Pbti Relaxation and Lifetime Extrapolationmentioning

confidence: 99%

Suitability of high-k gate oxides for III–V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Franco

Alian

Kaczer

et al. 2014

2014 IEEE International Reliability Physics Symposium

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“…However, the realistic stress conditions of the SRAM cells really depend on customer usages (workload). In [10][11][12][13], the authors estimated the SRAM degradation due to BTI based on the realistic stress conditions considering the actual workload. On the other hand, the impact of the HCI effect on SRAM stability is not as studied as BTI because BTI is usually dominant due to its frequency independence.…”

Section: Introductionmentioning

confidence: 99%

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

Liu¹,

Chen²,

Milor³

2018

Dependability Engineering

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The majority of transistors in a modern microprocessor are used to implement static random access memories (SRAM). Therefore, it is important to analyze the reliability of SRAM blocks. During the SRAM design, it is important to build in design margins to achieve an adequate lifetime. The two main wearout mechanisms that increase a transistor's threshold voltage are bias temperature instability (BTI) and hot carrier injections (HCI). BTI and HCI can degrade transistors' driving strength and further weaken circuit performance. In a microprocessor, first-level (L1) caches are frequently accessed, which make it especially vulnerable to BTI and HCI. In this chapter, the cache lifetimes due to BTI and HCI are studied for different cache configurations, namely, cache size, associativity, cache line size, and replacement algorithm. To give a case study, the failure probability (reliability) and the hit rate (performance) of the L1 cache in a LEON3 microprocessor are analyzed, while the microprocessor is running a set of benchmarks. Essential insights can be provided from our results to give better performance-reliability tradeoffs for cache designers.

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“…The related stochastic effects may lead to non-negligible device-to-device and time-to-time variations of the instability of individual devices. A good deal of effort has been devoted recently to account for the stochastic effects in the circuit simulation arising from the negative-bias-temperature instability (NBTI) of very small MOSFETs [6][7][8][9]. Those models rely on the 'atomistic' or 'defect-based' approach and are probabilistic in nature.…”

Section: Introductionmentioning

confidence: 99%

Compact model for parametric instability under arbitrary stress waveform

Alagi

Rossetti

Stella

et al. 2015

Solid-State Electronics

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Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM

Cited by 46 publications

References 17 publications

Suitability of high-k gate oxides for III–V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Suitability of high-k gate oxides for III–V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

Compact model for parametric instability under arbitrary stress waveform

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Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM

Cited by 46 publications

References 17 publications

Suitability of high-k gate oxides for III&#x2013;V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Suitability of high-k gate oxides for III&#x2013;V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

Compact model for parametric instability under arbitrary stress waveform

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Product

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Suitability of high-k gate oxides for III–V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>

Suitability of high-k gate oxides for III–V devices: A PBTI study in In<inf>0.53</inf>Ga<inf>0.47</inf>As devices with Al<inf>2</inf>O<inf>3</inf>