Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)
DOI: 10.1109/essderc.2003.1256843
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Deep trench isolation for a 50 V 0.35 μm based smart power technology

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Cited by 6 publications
(2 citation statements)
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“…The proposed approach has been applied to an industrial Power-On-Reset (POR) circuit ( Figure 5) designed in the 0.35 µm BCD technology I3T50 [21]. As shown in Figure 2, the defect-oriented test is applied by using a resistor-based fault model.…”
Section: Resultsmentioning
confidence: 99%
“…The proposed approach has been applied to an industrial Power-On-Reset (POR) circuit ( Figure 5) designed in the 0.35 µm BCD technology I3T50 [21]. As shown in Figure 2, the defect-oriented test is applied by using a resistor-based fault model.…”
Section: Resultsmentioning
confidence: 99%
“…D EEP trench isolation (DTI) is a commonly used isolation technique in bipolar [1], [2], [3], BiCMOS [4], [5] as well as CMOS technologies [6], [7], [8]. Apart from its advantages regarding parasitic capacitance [9], latch-up, and ESD robustness [10], it is often used as a guard ring for improved isolation between neighboring epitaxial regions.…”
Section: Introductionmentioning
confidence: 99%