Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL

We present a novel and highly automated technique for dynamic system level power management of System-on-aChip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs.There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a selfchecking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlesslycooperatebetweenhardwareandsoftwareconstraints to achieve maximum platform power optimization dynamically during execution.We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.

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“…In the context of low power verification, TRSs have been used to prove correctness of RT-level transformations [16].…”

Section: Introductionmentioning

confidence: 99%

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs

Viswanath¹,

Muralidhar

Seshadri

et al. 2013

International Symposium on Quality Electronic Design (ISQED)

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“…Functional verification is a processes used in order to demonstrate that the objectives of the design are preserved after its implementation [5]. In accordance with the state of the art, the power gating verification process has been executed at the Register-Transfer Level (RTL) [6][7][8][9], primarily, based on Common Power Format (CPF) and Unified Power Format (UPF) [10][11][12][13][14][15]. The purpose of this work is to demonstrate a SystemC simulator, open source, with support to functional verification of designs containing the principles of the power gating technique implemented in SystemC RTL.…”

Section: Introductionmentioning

confidence: 99%

Open SystemC Simulator with Support for Power Gating Design

Silveira

Brito

Oliveira

et al. 2012

International Journal of Reconfigurable Computing

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Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and the Unified Power Format (UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator is an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the retention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and accurate. Two case studies are presented to demonstrate the new features of that simulator.

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