Verification of Register Transfer Level Low Power Transformations

Karfa, Chandan; Mandal, Chittaranjan; Sarkar, Dipankar

doi:10.1109/isvlsi.2011.73

Cited by 2 publications

(1 citation statement)

References 6 publications

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“…However, design optimization for low power is most suitable before synthesis [6]. Eighty percent of Power Reduction opportunities are at the RTL stage (Fig 1) [7].…”

Section: Introductionmentioning

confidence: 99%

Fixing power bugs at RTL stage using PSL assertions

Purdy

Singh

Seli

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Power dissipation has now become the most critical design constraint. In the design flow of an SoC, power estimation and analysis usually come into the picture only after the completion of RTL synthesis. However, design optimization for low power is most suitable before synthesis. Each decrease in process geometry makes dynamic power targets harder to achieve. Also, changes made later in the design for power optimization lead to costly re-spin. It is better to pin-point power related problems in the design as early as possible when they can still be fixed. This also reduces risk by ensuring that the design meets power goals before embarking on its implementation. Our novel approach presented in this paper introduces power analysis at the RTL stage itself, using PSL assertions. This enables the SoC designer to optimize the design from a low power perspective at a very early stage (RTL) in the design flow, where the scope of modification is maximized and the cost minimized.

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“…However, design optimization for low power is most suitable before synthesis [6]. Eighty percent of Power Reduction opportunities are at the RTL stage (Fig 1) [7].…”

Section: Introductionmentioning

confidence: 99%