Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio

Seznec, André

doi:10.1109/isca.1994.288133

Cited by 86 publications

(73 citation statements)

References 10 publications

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“…Super-blocks, originally called sectors, have long used to reduce tag overhead [18] [7] [17]. A conventional super-block cache uses one tag to track multiple adjacent, aligned blocks, reducing tag area overhead at the cost of lower cache utilization due to internal fragmentation.Seznec's [7] Decoupled Sector Cache reduces internal fragmentation by decoupling the tags from the data blocks using backward pointers.…”

Section: Related Workmentioning

confidence: 99%

Skewed Compressed Caches

Sardashti

Seznec

Wood

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Cache compression seeks the benefits of a larger cache with the area and power of a smaller cache. Ideally, a compressed cache increases effective capacity by tightly compacting compressed blocks, has low tag and metadata overheads, and allows fast lookups. Previous compressed cache designs, however, fail to achieve all these goals.In this paper, we propose the Skewed Compressed Cache (SCC), a new hardware compressed cache that lowers overheads and increases performance. SCC tracks superblocks to reduce tag overhead, compacts blocks into a variable number of sub-blocks to reduce internal fragmentation, but retains a direct tag-data mapping to find blocks quickly and eliminate extra metadata (i.e., no backward pointers). SCC does this using novel sparse super-block tags and a skewed associative mapping that takes compressed size into account. In our experiments, SCC provides on average 8% (up to 22%) higher performance, and on average 6% (up to 20%) lower total energy, achieving the benefits of the recent Decoupled Compressed Cache [26] with a factor of 4 lower area overhead and lower design complexity.

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Section: Related Workmentioning

confidence: 99%

Skewed Compressed Caches

Sardashti

Seznec

Wood

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Prior approaches toward reducing metadata storage overhead have managed the DRAM cache using large cache lines on the order of kilobytes [1,4] or represented the presence of smaller sectors of a large cache block as a bit vector, eliminating the need to store full tag metadata [7,13]. These techniques still store metadata for all of DRAM, increasing bandwidth consumption and pollution of the DRAM cache, increasing false-sharing probability, and limiting scalability.…”

Section: Related Workmentioning

confidence: 99%

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Meza

Chang

Yoon

et al. 2012

IEEE Comput. Arch. Lett.

147

113

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Abstract-Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-change memory (PCM) can provide much larger storage capacity than traditional main memories. A key challenge for enabling high-performance and scalable hybrid memories, though, is efficiently managing the metadata (e.g., tags) for data cached in DRAM at a fine granularity. Based on the observation that storing metadata off-chip in the same row as their data exploits DRAM row buffer locality, this paper reduces the overhead of fine-granularity DRAM caches by only caching the metadata for recently accessed rows on-chip using a small buffer. Leveraging the flexibility and efficiency of such a fine-granularity DRAM cache, we also develop an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid memory with a 512MB DRAM cache, our proposal using an 8KB on-chip buffer can achieve within 6% of the performance of, and 18% better energy efficiency than, a conventional 8MB SRAM metadata store, even when the energy overhead due to large SRAM metadata storage is not considered.

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“…Sector caches [31,32] associate a single tag with a group of contiguous cache lines, allowing cache sizes to grow without paying the penalty of additional tag overhead. Sector caches use bandwidth efficiently by transferring only the needed cache lines within a sector.…”

Section: Related Workmentioning

confidence: 99%

“…Conventional sector caches [31] may result in worse utilization due to the space occupied by invalid cache lines within a sector. Decoupled sector caches [32] help reduce the number of invalid cache lines per sector by increasing the number of tags per sector. Compared to the Amoeba cache, the tag space is a constant overhead, and limits the # of invalid sectors that can be eliminated.…”

Section: Related Workmentioning

confidence: 99%

“…Sector caches have been used to [32,15] minimize bandwidth by fetching only sub-blocks but miss opportunities for spatial prefetching. Prefetching [17,29] may help reduce the miss rate for utilized sectors, but on applications with low-moderate or variable spatial locality, unused sectors due to misprediction, or unused regions within sectors, still pollute the cache and consume bandwidth.…”

Section: Introductionmentioning

confidence: 99%

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Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Kumar

Zhao

Shriraman

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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The fixed geometries of current cache designs do not adapt to the working set requirements of modern applications, causing significant inefficiency. The short block lifetimes and moderate spatial locality exhibited by many applications result in only a few words in the block being touched prior to eviction. Unused words occupy between 17-80% of a 64K L1 cache and between 1%-79% of a 1MB private LLC. This effectively shrinks the cache size, increases miss rate, and wastes on-chip bandwidth. Scaling limitations of wires mean that unused-word transfers comprise a large fraction (11%) of on-chip cache hierarchy energy consumption.We propose Amoeba-Cache, a design that supports a variable number of cache blocks, each of a different granularity. Amoeba-Cache employs a novel organization that completely eliminates the tag array, treating the storage array as uniform and morphable between tags and data. This enables the cache to harvest space from unused words in blocks for additional tag storage, thereby supporting a variable number of tags (and correspondingly, blocks). Amoeba-Cache adjusts individual cache line granularities according to the spatial locality in the application. It adapts to the appropriate granularity both for different data objects in an application as well as for different phases of access to the same data. Overall, compared to a fixed granularity cache, the Amoeba-Cache reduces miss rate on average (geometric mean) by 18% at the L1 level and by 18% at the L2 level and reduces L1-L2 miss bandwidth by 46%. Correspondingly, Amoeba-Cache reduces on-chip memory hierarchy energy by as much as 36% (mcf) and improves performance by as much as 50% (art).

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Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio

Cited by 86 publications

References 10 publications

Skewed Compressed Caches

Skewed Compressed Caches

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

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