Skewed Compressed Caches

Sardashti, Somayeh; Seznec, André; Wood, David А.

doi:10.1109/micro.2014.41

Cited by 53 publications

(66 citation statements)

References 26 publications

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“…Afterwards, the most probable elements are coded with [8, 10, 12, 16, 17, 23, 28, 29, 35, 40, 48-50, 52, 53, 56, 63, 64, 66, 78, 82, 83, 88, 93] Zero-content compression [14,35,41,50,52,57,62,78,81] Frequent value compression (FVC) [35,52,59,60,67,70] Base delta immediate (BDI) compression [16,23,35,48,51,63,83,93,94] LZ and variants [6,7,9,17,19,20,22 [8,12] Compression in GPUs [89,93,94] Use of compiler [9,21,43,44,72,73,93] fewer number of bits than those which are least probable. Thus, Huffman coding uses a variablelength coding scheme.…”

Section: Compression Algorithmsmentioning

confidence: 99%

“…Sardashti et al [62] also propose skewed compressed cache (SCC) which uses superblocks to reduce tag overhead and fragmentation but overcomes the limitation of DCC of extra metadata and latency by retaining a direct tag-data mapping. Their technique uses sparse super-block tags which can track anywhere between one block to all blocks in a superblock, depending on their compressibility.…”

Section: Techniques For Cachementioning

confidence: 99%

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A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

Mittal

Vetter

2016

IEEE Trans. Parallel Distrib. Syst.

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As the number of cores on a chip increase and key applications become even more data-intensive, memory systems in modern processors have to deal with increasingly large amount of data. In face of such challenges, data compression presents as a promising approach to increase effective memory system capacity and also provide performance and energy advantages. This paper presents a survey of techniques for using compression in cache and main memory systems. It also classifies the techniques based on key parameters to highlight their similarities and differences. It discusses compression in CPUs and GPUs, conventional and non-volatile memory (NVM) systems, and 2D and 3D memory systems. We hope that this survey will help the researchers in gaining insight into the potential role of compression approach in memory components of future extreme-scale systems.

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Section: Compression Algorithmsmentioning

confidence: 99%

Section: Techniques For Cachementioning

confidence: 99%

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

Mittal

Vetter

2016

IEEE Trans. Parallel Distrib. Syst.

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“…Several compression mechanisms have been proposed in the literature to increase the effective storage capacity of all the on-chip cache levels, potentially reducing misses and improving performance [2], [13], [16], [22], [34], [36], [40]. In general, these proposals seek to maximize the compression ratio either to store more than one block in each cache entry, or to reduce the energy consumption of each LLC access.…”

Section: Related Workmentioning

confidence: 99%

“…Thus, blocks might need to be shifted properly before insertion [2], [34]. This issue can be overcome by using sparse super-block tags and a skewed associative mapping [36]. Nevertheless, Concertina does not have this problem, as only one block is stored per cache entry.…”

Section: Writeback Handlingmentioning

confidence: 99%

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

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Abstract-Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100% of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression-and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2%, even when using small SRAM cells, which implies over 90% of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.

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“…This is because, in conventional caches each block needs a separate tag. We can reduce the tag area overheads by storing compressed blocks only from neighboring addresses [15], [16], [17], [18]. This enables us to use a single overlapping tag for all compressed blocks.…”

Section: Introductionmentioning

confidence: 99%

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

Hong

Nair

Abali

et al. 2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Compression is seen as a simple technique to increase the effective cache capacity. Unfortunately, compression techniques either incur tag area overheads or restrict data placement to only include neighboring compressed cache blocks to mitigate tag area overheads. Ideally, we should be able to place arbitrary compressed cache blocks without any placement restrictions and tag area overheads. This paper proposes Touché, a framework that enables storing multiple arbitrary compressed cache blocks within a physical cacheline without any tag area overheads. The Touché framework consists of three components. The first component, called the "Signature" (SIGN) engine, creates shortened signatures from the tag addresses of compressed blocks. Due to this, the SIGN engine can store multiple signatures in each tag entry. On a cache access, the physical cacheline is accessed only if there is a signature match (which has a negligible probability of false positive). The second component, called the "Tag Appended Data" (TADA) mechanism, stores the full tag addresses with data. TADA enables Touché to detect false positive signature matches by ensuring that the actual tag address is available for comparison. The third component, called the "Superblock Marker" (SMARK) mechanism, uses a unique marker in the tag entry to indicate the occurrence of compressed cache blocks from neighboring physical addresses in the same cacheline. Touché is completely hardware-based and achieves an average speedup of 12% (ideal 13%) when compared to an uncompressed baseline.

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Skewed Compressed Caches

Cited by 53 publications

References 26 publications

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

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