Debug enhancements in assertion-checker generation

Boulé, Marc; Chenard, J.-S.; Žilić, Željko

doi:10.1049/iet-cdt:20060209

Cited by 25 publications

(13 citation statements)

References 6 publications

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“…In future, this work can be expanded for incorporation with multiprocessor design [41][42] [43], for enhancing debug features [44], in reliable networks on chip [45][46], as well as reversible [47], embedded high-density memory [48] design, and the extension is possible with transform-based techniques under lack of available data [49]. Finally, the low-power [50] and the sequential design test [51] can be applied.…”

Section: Future Workmentioning

confidence: 99%

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

Najafi

Banville²,

Hafed³

et al. 2013

Analog Integr Circ Sig Process

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High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This thesis investigates techniques to speed up bit-error rate (BER) and jitter testing of HSSI devices.This work proposes an oversampling-based transmitter test scheme that accelerates transmitter jitter as well as eye diagram testing through the deployment of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed.We aim to accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds. This exceeds the performance of [2], which by itself was an improvement from seconds to 100 ms.ii

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Section: Future Workmentioning

confidence: 99%

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

Najafi

Banville²,

Hafed³

et al. 2013

Analog Integr Circ Sig Process

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“…Using a similar approach for post-silicon validation has been successfully deployed for microprocessors [1]. Nonetheless, for generic circuits, though there are known techniques to implement assertions into hardware [2], it is less obvious how one can port constrained-random stimuli in a systematic manner.…”

Section: Motivationmentioning

confidence: 99%

On-chip stimuli generation for post-silicon validation

Nicolici

2012

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)

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In contrast to pre-silicon verification environments, insystem validation is not strongly constrained by the number of stimuli that can be applied; rather, the quality of the patterns, as well as the observation of the events of interest are the real concern. This paper motivates the need for developing structured methods for porting the controllability aspects of pre-silicon verification into post-silicon validation environments. Use cases and challenges for such methods are outlined.

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“…The unit is a state machine that can be generated from the description with formal languages for assertion-based verification. Later, the same authors [5] introduced several enhanced features to localize the errors that are buried as internal states in sophisticated assertions, in addition to reduce the associated hardware cost in unit generation in [4],.…”

Section: Trace-based Debug Controlmentioning

confidence: 99%