Dead‐time optimisation for a phase‐shifted dc–dc full bridge converter with GaN HEMT

Abstract

An accurate dead-time adjustment method for phase-shifted full bridge (PSFB) converter is presented. This method allows the dead-time of converters to be optimised to meet zero voltage switching condition. The optimum dead-time range can be predicted with high accuracy for any type of power semiconductor switch, including gallium nitride high-electron-mobility transistor, so that a practical design for a PSFB converter can be realised. The validity of the proposed deadtime optimisation method was verified by experimental results with a 600 W prototype.

General multi‐mode control method for optimising the efficiency of full bridge converter based on prominent control modes and transition points calculation

“…The fullbridge switching converter topology is the most widely used one, for applications with medium-to-high power consumptions, in the industry. Achieving higher efficiency for load variations over different and/or wider load sub-ranges is the subject of many recent researches [9][10][11][12][13][14][15][16][17][18][19][20]. Still, improving the efficiency for wider load variations, from no-load to full-load, is important and desired for many applications, including server computer systems, electric vehicles, battery chargers and so on, and is one of the aims here.…”

“…On the other hand, some studies propose the change of control method subject to the load variations, for efficiency improvement [11][12][13][14][15][16][17][18][19][20]. Among them, [11,12] propose to change the phase shift control mode into the pulse width modulation (PWM) control mode, in order to reduce the circulating current losses under the light load condition.…”

“…Among them, [11,12] propose to change the phase shift control mode into the pulse width modulation (PWM) control mode, in order to reduce the circulating current losses under the light load condition. In [13,14] with the aim of increasing the converter efficiency at the heavy load, phase shift delay time is adjusted according to the load current. In [15][16][17], by widening the phase shift delay time under the light load condition, the switching occurs at a lower drain-source voltage; therefore, switching losses can be reduced under the light load condition.…”

Design of Full-bridge DC-DC Converter 311/100 V 1kW with PSPWM Method to Get ZVS Condition

“…While the current depends on the load. Therefore, by making the design, method and selection of components for correct and appropriate converter loading area, it is expected to significantly reduce the switching losses and losses in the converter as a whole [12], [13], [16], [17].…”

“…The aim of that method is to get zero voltage switching (ZVS) condition, at the time of the switch turn-on, the switch will be active when the voltage value is zero. So that the power loss in the switching process can be minimized [2], [16], [17]. The parameters that must be satisfied in order to achieve the ZVS condition are leakage inductance in a sufficient value, deadtime as small as possible and current which is greater than the value required.…”