DDD-FM9001: Derivation of a verified microprocessor

Bose, Bhaskar; Johnson, Steven D.

doi:10.1007/bfb0021724

Cited by 22 publications

(11 citation statements)

References 9 publications

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“…Johnson and his colleagues have used this approach to derive implementations of the FM8501 and FM9001 processors due to Hunt [Bose and Johnson 1993], a PCI bus interface and a Java byte code generation core. They claim that this is a useful technique for circuits with high algorithmic complexity.…”

Section: Hardware Synthesis From First-order Recursion Equationsmentioning

confidence: 99%

Synchronous digital circuits as functional programs

Gammie

2013

ACM Comput. Surv.

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Functional programming techniques have been used to describe synchronous digital circuits since the early 1980s. Here we survey the systems and formal underpinnings that constitute this tradition. We situate these techniques with respect to other formal methods for hardware design and discuss the work yet to be done.Hardware designs traverse a series of abstraction layers: what might begin as a highlevel behavioural model that addresses architectural issues will, when mature, typically be manually translated into a Register-Transfer Level (RTL) description that captures how the high-level computations are performed by the finite-state means of logic gates and memories. This is typically validated against the original model using simulation and testing, or more formally with model-checking techniques or a proof assistant. The resulting netlists (circuit schematics represented as graphs) are semiautomatically mapped to an implementation technology and laid out for realisation in silicon.The original motivation for developing Domain-Specific Languages (DSLs) [Mernik et al. 2005] for the upper reaches of this process was to harness the huge increases in transistor densities on silicon chips forecast by Moore's law [Mead and Conway 1980]. It was hoped that productivity would rise with the abstraction level, yielding designs that were more reusable, scalable, and correct. Traditional imperative programming languages were a poor fit, as their implicit sequentiality conflicts with the intrinsic parallelism of hardware, and a global store is in tension with the ideal of placing computations physically near the relevant state [Nikhil 2011]. For these reasons, I thank

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Section: Hardware Synthesis From First-order Recursion Equationsmentioning

confidence: 99%

Synchronous digital circuits as functional programs

Gammie

2013

ACM Comput. Surv.

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“…Landin's SECD machine [Lan63] has been considered in [Gra92,BiG90]. [Hun89,Hun92,Hun94] discuss a PDP-11-based processor and a more advanced successor, also considered in [BoJ93].…”

Section: Related Workmentioning

confidence: 99%

Algebraic Models of Correctness for Microprocessors

Fox

Harman

2000

Form. Asp. Comput.

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We present a method of describing microprocessors at different levels of temporal and data abstraction, and consider pipelined and superscalar processors. We model microprocessors using iterated maps, defined by equations which evolve a system from an initial state by the iterative application of a nextstate function. Levels of timing abstraction are related by temporal abstraction maps called retimings. We state correctness conditions for microprogrammed, pipelined and superscalar processors. We introduce one-step theorems that permit verification of correctness conditions to be considerably simplified under well-defined conditions. We extend the one-step theorems to superscalar microprocessors.

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“…Refinement techniques such as the above should be contrasted with techniques of program transformation, particularly for hardware (e.g., Bose and Johnson [1993]). In these styles a correct functionality is first written down in a functional or logic programming language, and then an efficient coding is derived via a suite of semantics-preserving transformations.…”

Section: Introductionmentioning

confidence: 97%

A refinement calculus for the synthesis of verified hardware descriptions in VHDL

Breuer

Delgado

Marín

et al. 1997

ACM Trans. Program. Lang. Syst.

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A formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is ''correct by construction." The calculus is closely related to a Hoare-style programming logic for VHDL and real-time systems in general. That logic and a semantics for a core subset of VHDL are described. The programming logic and the associated refinement calculus are shown to be complete. This means that if there is a code that can be shown to implement a given specification, then it will be derivable from the specification via the calculus.

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DDD-FM9001: Derivation of a verified microprocessor

Cited by 22 publications

References 9 publications

Synchronous digital circuits as functional programs

Synchronous digital circuits as functional programs

Algebraic Models of Correctness for Microprocessors

A refinement calculus for the synthesis of verified hardware descriptions in VHDL

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