Algebraic Models of Correctness for Microprocessors

Abstract

We present a method of describing microprocessors at different levels of temporal and data abstraction, and consider pipelined and superscalar processors. We model microprocessors using iterated maps, defined by equations which evolve a system from an initial state by the iterative application of a nextstate function. Levels of timing abstraction are related by temporal abstraction maps called retimings. We state correctness conditions for microprogrammed, pipelined and superscalar processors. We introduce one-step theorems that permit verification of correctness conditions to be considerably simplified under well-defined conditions. We extend the one-step theorems to superscalar microprocessors.

Formal Specification and Verification of ARM6

“…The invariance condition captured by the initialisation function is only required to hold at times given by a temporal abstraction map. For a more detailed account the reader is referred to [7,8].…”

“…An algebraic framework for carrying out processor verifications [12,7] was used as the basis for the ARM6 verification. Systems are modelled with state functions: these are functions of the form F : T × A → A, where T = {0, 1, .…”

Verifying a Simple Pipelined Microprocessor Using Maude

“…5.4 and [9,7]) to reduce formal verification to state exploration. In this paper, we do not consider input and output: however, they are easily accommodated [15,7].…”

“…In [14,15] mathematical models of microprogrammed examples are considered. In [9,11], correctness models and the formal verification process are examined. In [8,10] models of superscalar processors are examined by means of a substantial example.…”

“…Commonly, in pipelined systems, state elements in the specification are viewed as distributed in time in the implementation. We regard specification states as [some function of] state elements in the implementation at a single point in time (see [9,7]). In addition, time is explicitly present in our model.…”