DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design

Abstract

The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until nowcircuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deepsubmicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -both for digital as well as for analog -is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results -best/worst case and OCV (On Chip Variation) factor -for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.

Semiconductor Manufacturing Final Test Yield Optimization and Wafer Acceptance Test Parameter Inverse Design Using Multi-Objective Optimization Algorithms

“…Previous studies on semiconductor yield optimization mainly focus on the IC front-end design instead of using production data for yield improvement. The purpose of design phase yield optimization is to avoid expensive redesign and redo the development and manufacturing process chain [2]. The common method for design phase yield optimization is based on yield model simulation using defect distribution and sensitivity.…”

Interpreting SSTA Results with Correlation

“…However, statistical timing techniques have not been widely adopted. First, as suggested in [5], the accuracy of published approaches is not clear due to the fact that Monte-Carlo (MC) simulations used for validations are based on the same assumptions used in SSTA. Next, the dependency of gate delay on input slope and output load has not received much attention [5].…”

“…First, as suggested in [5], the accuracy of published approaches is not clear due to the fact that Monte-Carlo (MC) simulations used for validations are based on the same assumptions used in SSTA. Next, the dependency of gate delay on input slope and output load has not received much attention [5]. In fact, most of the proposed approaches either make a worst-case estimate of slope, or propagate the latest arriving slope, each of which can lead to significant error of estimation [6].…”