Myanmar is experiencing an HIV epidemic documented since the late 1980s. The National AIDS Programme national surveillance ante-natal clinics had already estimated in 1993 that 1.4% of pregnant women were HIV positive, and UNAIDS estimates that at end 2005 1.3% (range 0.7–2.0%) of the adult population was living with HIV. While a HIV surveillance system has been in place since 1992, the programmatic response to the epidemic has been slower to emerge although short- and medium-terms plans have been formulated since 1990. These early plans focused on the health sector, omitted key population groups at risk of HIV transmission and have not been adequately funded. The public health system more generally is severely under-funded.By the beginning of the new decade, a number of organisations had begun working on HIV and AIDS, though not yet in a formally coordinated manner. The Joint Programme on AIDS in Myanmar 2003–2005 was an attempt to deliver HIV services through a planned and agreed strategic framework. Donors established the Fund for HIV/AIDS in Myanmar (FHAM), providing a pooled mechanism for funding and significantly increasing the resources available in Myanmar. By 2006 substantial advances had been made in terms of scope and diversity of service delivery, including outreach to most at risk populations to HIV. More organisations provided more services to an increased number of people. Services ranged from the provision of HIV prevention messages via mass media and through peers from high-risk groups, to the provision of care, treatment and support for people living with HIV. However, the data also show that this scaling up has not been sufficient to reach the vast majority of people in need of HIV and AIDS services.The operating environment constrains activities, but does not, in general, prohibit them. The slow rate of service expansion can be attributed to the burdens imposed by administrative measures, broader constraints on research, debate and organizing, and insufficient resources. Nevertheless, evidence of recent years illustrates that increased investment leads to more services provided to people in need, helping them to obtain their right to health care. But service expansion, policy improvement and capacity building cannot occur without more resources.
The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until nowcircuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deepsubmicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -both for digital as well as for analog -is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results -best/worst case and OCV (On Chip Variation) factor -for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will be presented. The combination of event driven and bitparallel simulation allows for high accuracy due to the real delay model of the former while maintaining the speedup of the latter. This is demonstrated by detailed experimental results.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.