Data retention voltage analysis of various low-power SRAM topologies

Leochico, Kester; John, Eugene

doi:10.1109/mwscas.2014.6908564

Cited by 5 publications

(2 citation statements)

References 14 publications

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“…The distribution of DRV for different bitcells shows how much intra-die variation change the effective DRV limit. To understand the rationale behind the DRV variation across different bitcells, we characterize the effect of the different devices on DRV by varying their VT and measuring the sensitivity of the DRV to this change [10]. Fig.…”

Section: A Reliabilitymentioning

confidence: 99%

Optimizing SRAM bitcell reliability and energy for IoT applications

Patel

Yahya

Calhoun

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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This paper compares six different 8T SRAM bitcells targeting different design space requirements -such as reliability and low power/energy -for Internet of Things (IoT) applications. Different bitcells leverage the varying characteristics of highthreshold (high-VT) and standard-threshold (standard-VT) devices to affect SRAM metrics like write margin (WM), Data Retention Voltage (DRV), Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM), write and read energy, standby leakage power, and variability. The reliability for each bitcell over process (intra-and inter-die variation) and temperature variation is also evaluated. Measured results for a commercial 130nm test chip compare the most promising two 8T bitcell structures targeting low leakage and low energy.

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Section: A Reliabilitymentioning

confidence: 99%

Optimizing SRAM bitcell reliability and energy for IoT applications

Patel

Yahya

Calhoun

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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“…For this reason, we divide evaluation metrics into two categories: reliability and dynamic metrics. on DRV by varying their V T and measuring the sensitivity of the DRV to this change [46].…”

Section: Comparison Of Evaluation Metricsmentioning

confidence: 99%

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Patel¹

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The number of ubiquitous sensors has increased to more than double the human population and is expected to continue growing in the future. The pervasive use of sensors for applications such as personal healthcare and the Internet of Things (IoT) presents a growing sustainability challenge concerning the availability and accessibility of power sources. With 50 billion less BSN system. First, we explore different design knobs for an optimal SRAM design targeting ULP applications. These knobs include leveraging advanced fabrication technology, optimal device selection, circuit design techniques, and architectural techniques. Next, we evaluate the efficacy of different read and write peripheral assist techniques for improving reliability and energy efficiency of subthreshold SRAMs and provide stability, power, and performance trade-offs for system level optimization. The result of various optimization approaches resulted in a leakage and energy optimized SRAM operating over with leakage power reduced to 1.5 pW/bit while consuming only 6.24 pJ/access energy that is 40% more efficient than the previous version. To address a wide range of IoT applications with energy optimization, we propose a Canary sensor based minimum supply voltage (V M IN) tracking with optimal selection of the peripheral assist techniques. Later, we address the reliability issue at subthreshold operation using a process, voltage, and temperature (PVT) variation mitigation controller. Finally, the impact of the radiation-induced soft error is evaluated to provide a comprehensive study on reliability for the ULP SRAM at scaled V DD. Dedicating what all I learn in my life to 'Gurus' in my life-for enlightening my life with the knowledge, My Parents-for always giving me the courage to achieve impossible, My Wife-Pooja-for her unwavering love and motivation Meaning: Lead me from the unreal to the real; from darkness(ignorance) to light(knowledge); and from death to immortality. iv v Besides my life at the lab doing the research work, I immensely enjoyed my stay in Charlottesville. I am very much grateful to my neighbors for their pleasant company during my stay. I am also grateful to the members of Swadhyay Parivar for their selfless love. Last but never the least, I would like to thank my family members. I am very grateful for my parents, Naranbhai and Induben, for their continuous support and motivation for vii pursuing higher education. Especially, I thank my mother for always keeping me in her prayer while my father for giving me the courage to achieve whatever seems impossible to me. I thank my sister-Rinku-for her sisterly love. I cannot encompass my gratitude to my wife, Pooja, with the words for her support. She always been a lovely wife with continuous support. I am also indebted to almighty God for his blessing of two beautiful children, Samyak and Swara-my best stress busters! I cannot image myself completing my Ph.D. without the help of all these three-my wife and my kids-Thank you so much!

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Optimization of area and power in multi-mode power gating scheme for static memory elements

2016

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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Data retention voltage analysis of various low-power SRAM topologies

Cited by 5 publications

References 14 publications

Optimizing SRAM bitcell reliability and energy for IoT applications

Optimizing SRAM bitcell reliability and energy for IoT applications

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Optimization of area and power in multi-mode power gating scheme for static memory elements

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