Optimizing SRAM bitcell reliability and energy for IoT applications

Patel, Harsh; Yahya, Farah B.; Calhoun, Benton H.

doi:10.1109/isqed.2016.7479149

Cited by 27 publications

(14 citation statements)

References 11 publications

(9 reference statements)

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“…Moreover, in the sub-threshold region, the drain current, which exponentially depends upon the threshold voltage (V th ), introduces numerous challenges such as high standby power, low read and hold stability and read failure. Nevertheless, the low read and write stability are also major factors that resist conventional SRAM architectures to work in the sub-threshold region [4]. Due to the rapid growth of the Internet market, the IoT brings connectivity, communication, and data gathering to existing devices.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, SRAM is preferred as a cache memory due to its faster response. Moreover, the robustness of such memory systems with respect to the variations in process-voltage-temperature (PVT) values of metal oxide semiconductor devices (MOS) and power efficiency are two of the most important design constraints [4]. As per the literature, more than 40% of the active energy is consumed due to the leakage current in modern high-performance processors [6,7].…”

Section: Introductionmentioning

confidence: 99%

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Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh

Vishvakarma

2017

JLPEA

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Abstract:In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high static and dynamic noise margins. The IoT application requires battery-enabled low leakage memory architecture in a subthreshold regime. Therefore, to improve leakage power consumption and provide better cell stability, a power-gated robust 10T SRAM is presented in this paper. The proposed cell uses a power-gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the stacking of n-MOS transistors in 10T SRAM latch and by separating the read path from the 10T SRAM latch, the static and dynamic noise margins in read and write operations has shown significant tolerance w.r.t. the variations in device process, voltage, and temperature (PVT) values. The proposed SRAM shows significantly improved performance in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write ability or write trip point (WTP), read-write energy, and dynamic read margin (DRM). Furthermore, these parameters of the proposed cell are observed at 8-Kilo bit (Kb) SRAM and compared with existing SRAM architectures. From the Monte Carlo simulation results, it is observed that the leakage power of a proposed low threshold voltage-LVT 10T SRAM is reduced by 98.76%, 98.6%, 6.7%, and 98.2% as compared to the LVT C6T, RD8T, LP9T, and ST10T SRAM, respectively, at 0.3V VDD. Additionally, in the proposed 10T SRAM, parameters such as RSNM, WSNM, WTP, and DRM are improved by 3×, 2×, 1.11×, and 1.32×, respectively, as compared to C6T SRAM. Similarly, the proposed 10T SRAM shows an improvement of 1.48×, 1.25×, and 1.1× in RSNM, WSNM, and WTP, respectively, in the parameters as compared to RD8T SRAM at 0.3 V VDD.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh

Vishvakarma

2017

JLPEA

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“…Since, conventional non-volatile memories consume higher read and write power, the scaling of supply voltages and the techniques to reduce leakage at sub-threshold voltages needed. However, the low cell stability is also one of the factor which defy conventional SRAM architecture to not to work at sub-threshold region [4].However, due to rapid growth of internet market through all over the world, Internet of Things (IoT) brings connectivity, communication, and data gathering to existing devices. IoT includes countless devices connected and communicated with each other to enrich the present lifestyle, and its applicability ranges widely from traditional internet to industrial internet and also to consumer internet [5].…”

mentioning

confidence: 99%

“…Therefore, SRAM is always preferred to be used as cache memory due to its faster response. Moreover, the robustness of such memory systems, for the variations in environmental conditions and power efficiency are two of the most important design constraints [4]. As per the literature, more than 40% of the active energy is consumed due to the leakage currents in modern high performance processors [6,7].…”

mentioning

confidence: 99%

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh¹,

Vishvakarma²

2017

Preprint

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An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.Keywords: power gating; read decoupling; read-write static noise margin; dynamic noise margin; read-write energy; schmitt trigger; leakage power. IntroductionThe massive constrain headed for internet of things (IoT) devices has led to developments of ultra-low power (ULP) systemson-chip (SoCs) that are capable of operating in sub-threshold voltages [1,2]. One way to guarantee low power and energy consumption is to scale down the supply voltage to the sub-threshold region [3]. However, the reduced on-to-off current ratio (I ON /I OFF ) and the exponential dependence of the current on the threshold voltage (V th ) in the sub-threshold region introduces many challenges especially in rationed circuits such as the traditional 6T static random access memory (SRAM) bit-cell. Since, conventional non-volatile memories consume higher read and write power, the scaling of supply voltages and the techniques to reduce leakage at sub-threshold voltages needed. However, the low cell stability is also one of the factor which defy conventional SRAM architecture to not to work at sub-threshold region [4].However, due to rapid growth of internet market through all over the world, Internet of Things (IoT) brings connectivity, communication, and data gathering to existing devices. IoT includes countless devices connected and communicated with each other to enrich the present lifestyle, and its applicabi...

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“…In [24], the authors showed the significant reduction in I ON -to-I OF F ratio and higher variation across process corners that led to stability and performance degradation of an SRAM. In addition to technology scaling, V DD has been scaled down significantly to minimize the active energy (CV 2 DD ) [17] for ULP IoTs applications.…”

Section: Subthreshold Sram Design Challengesmentioning

confidence: 99%

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Patel¹

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The number of ubiquitous sensors has increased to more than double the human population and is expected to continue growing in the future. The pervasive use of sensors for applications such as personal healthcare and the Internet of Things (IoT) presents a growing sustainability challenge concerning the availability and accessibility of power sources. With 50 billion less BSN system. First, we explore different design knobs for an optimal SRAM design targeting ULP applications. These knobs include leveraging advanced fabrication technology, optimal device selection, circuit design techniques, and architectural techniques. Next, we evaluate the efficacy of different read and write peripheral assist techniques for improving reliability and energy efficiency of subthreshold SRAMs and provide stability, power, and performance trade-offs for system level optimization. The result of various optimization approaches resulted in a leakage and energy optimized SRAM operating over with leakage power reduced to 1.5 pW/bit while consuming only 6.24 pJ/access energy that is 40% more efficient than the previous version. To address a wide range of IoT applications with energy optimization, we propose a Canary sensor based minimum supply voltage (V M IN) tracking with optimal selection of the peripheral assist techniques. Later, we address the reliability issue at subthreshold operation using a process, voltage, and temperature (PVT) variation mitigation controller. Finally, the impact of the radiation-induced soft error is evaluated to provide a comprehensive study on reliability for the ULP SRAM at scaled V DD. Dedicating what all I learn in my life to 'Gurus' in my life-for enlightening my life with the knowledge, My Parents-for always giving me the courage to achieve impossible, My Wife-Pooja-for her unwavering love and motivation Meaning: Lead me from the unreal to the real; from darkness(ignorance) to light(knowledge); and from death to immortality. iv v Besides my life at the lab doing the research work, I immensely enjoyed my stay in Charlottesville. I am very much grateful to my neighbors for their pleasant company during my stay. I am also grateful to the members of Swadhyay Parivar for their selfless love. Last but never the least, I would like to thank my family members. I am very grateful for my parents, Naranbhai and Induben, for their continuous support and motivation for vii pursuing higher education. Especially, I thank my mother for always keeping me in her prayer while my father for giving me the courage to achieve whatever seems impossible to me. I thank my sister-Rinku-for her sisterly love. I cannot encompass my gratitude to my wife, Pooja, with the words for her support. She always been a lovely wife with continuous support. I am also indebted to almighty God for his blessing of two beautiful children, Samyak and Swara-my best stress busters! I cannot image myself completing my Ph.D. without the help of all these three-my wife and my kids-Thank you so much!

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Optimizing SRAM bitcell reliability and energy for IoT applications

Cited by 27 publications

References 11 publications

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

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