Data compression for system-on-chip testing using ATE

Karimi, F.; Meleis, Waleed; Navabi, Zainalabedin; Lombardi, Fabrizio

doi:10.1109/dftvs.2002.1173513

Cited by 9 publications

(2 citation statements)

References 12 publications

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“…Various methods have thus been proposed for compression of test data Yamaguchi et al, 2002;Karimi et al, 2002). The asymmetry between the decoding and encoding time of the BWT makes it particularly suited for compression under the ATE environment, where very fast and simple decompression is needed, but encoding is only done once, and can be done on a fast system.…”

Section: Test Data Compressionmentioning

confidence: 99%

The Burrows-Wheeler Transform: Data Compression, Suffix Arrays, and Pattern Matching

2008

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Section: Test Data Compressionmentioning

confidence: 99%

The Burrows-Wheeler Transform: Data Compression, Suffix Arrays, and Pattern Matching

2008

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“…In the compression method that we are using for our architecture (test reuse [9]) the test set is partitioned and the repeated segments of test set are removed. To reduce the amount of test data, this technique removes the data that is left unchanged from one test to another.…”

Section: A Data Compressionmentioning

confidence: 99%

A Low-Power Scan-Path Architecture

Hatami

Alisafaee²,

Atoofian³

et al.

2005 IEEE International Symposium on Circuits and Systems

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In this paper, we propose a scan cell architecture that decreases power consumption and the total consumed energy. In the method which is based on the data compression, the test vector set is divided into two repeated and unrepeated partitions. The repeated part, which is common among some of the vectors, is not changed during the new scan path where new test vector will be filled. This way, every time that a new test vector is applied to the circuit, only the cells of the scan-path which are not repeated are altered and other cells retain their values. As a result, the test vector is applied to the circuit under test in a fewer number of clock cycles. In addition, the values of some scan cells remain unchanged leading to a lower switching activity in the scan-path during test mode. Besides, by latching the inputs of circuit under test, the proposed scan chain architecture avoids transitioning of test vectors into the circuit inputs at the time of shifting.This also saves power of the system during the test mode. Our architecture has been applied to ISCAS89 circuits. Simulation results reveal up to 66% reduction in the test power consumption when compared to the conventional scan-path architecture.

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Test Compression

Navabi

2010

Digital System Test and Testable Design

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Data compression for system-on-chip testing using ATE

Cited by 9 publications

References 12 publications

The Burrows-Wheeler Transform: Data Compression, Suffix Arrays, and Pattern Matching

The Burrows-Wheeler Transform: Data Compression, Suffix Arrays, and Pattern Matching

A Low-Power Scan-Path Architecture

Test Compression

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