2005 IEEE International Symposium on Circuits and Systems
DOI: 10.1109/iscas.2005.1465826
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A Low-Power Scan-Path Architecture

Abstract: In this paper, we propose a scan cell architecture that decreases power consumption and the total consumed energy. In the method which is based on the data compression, the test vector set is divided into two repeated and unrepeated partitions. The repeated part, which is common among some of the vectors, is not changed during the new scan path where new test vector will be filled. This way, every time that a new test vector is applied to the circuit, only the cells of the scan-path which are not repeated are … Show more

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Cited by 2 publications
(2 citation statements)
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“…Architectural testing is divided into two parts [14]. The first part is to test the activation function that is most suitable for precipitation prediction cases [15].…”
Section: Architecture Testingmentioning
confidence: 99%
“…Architectural testing is divided into two parts [14]. The first part is to test the activation function that is most suitable for precipitation prediction cases [15].…”
Section: Architecture Testingmentioning
confidence: 99%
“…A pattern-filtering technique is combined with Hertwig and Wunderlich's technique to avoid scan-path activity during scan shifting in [36]. Hatami et al [37] proposed a scan cell architecture that decreases power consumption and the total consumed energy. In the method which is based on the data compression, the test vector set is divided into two repeated and unrepeated partitions.…”
Section: By Filtering Unnecessary Vectorsmentioning
confidence: 99%