A Low-Power Scan-Path Architecture

Abstract

In this paper, we propose a scan cell architecture that decreases power consumption and the total consumed energy. In the method which is based on the data compression, the test vector set is divided into two repeated and unrepeated partitions. The repeated part, which is common among some of the vectors, is not changed during the new scan path where new test vector will be filled. This way, every time that a new test vector is applied to the circuit, only the cells of the scan-path which are not repeated are altered and other cells retain their values. As a result, the test vector is applied to the circuit under test in a fewer number of clock cycles. In addition, the values of some scan cells remain unchanged leading to a lower switching activity in the scan-path during test mode. Besides, by latching the inputs of circuit under test, the proposed scan chain architecture avoids transitioning of test vectors into the circuit inputs at the time of shifting.This also saves power of the system during the test mode. Our architecture has been applied to ISCAS89 circuits. Simulation results reveal up to 66% reduction in the test power consumption when compared to the conventional scan-path architecture.

Rainfall prediction using artificial neural network with historical weather data as supporting parameters

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Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

“…A pattern-filtering technique is combined with Hertwig and Wunderlich's technique to avoid scan-path activity during scan shifting in [36]. Hatami et al [37] proposed a scan cell architecture that decreases power consumption and the total consumed energy. In the method which is based on the data compression, the test vector set is divided into two repeated and unrepeated partitions.…”