Damage-Free Smooth-Sidewall InGaAs Nanopillar Array by Metal-Assisted Chemical Etching

Abstract

Producing densely packed high aspect ratio InGaAs nanostructures without surface damage is critical for beyond Si-CMOS nanoelectronic and optoelectronic devices. However, conventional dry etching methods are known to produce irreversible damage to III-V compound semiconductors because of the inherent high-energy ion-driven process. In this work, we demonstrate the realization of ordered, uniform, array-based InGaAs pillars with diameters as small as 200 nm using the damage-free metal-assisted chemical etching (MacEtch) technology combined with the post-MacEtch digital etching smoothing. The etching mechanism of InGaAs is explored through the characterization of pillar morphology and porosity as a function of etching condition and indium composition. The etching behavior of InGaAs, in contrast to higher bandgap semiconductors (e.g., Si or GaAs), can be interpreted by a Schottky barrier height model that dictates the etching mechanism constantly in the mass transport limited regime because of the low barrier height. A broader impact of this work relates to the complete elimination of surface roughness or porosity related defects, which can be prevalent byproducts of MacEtch, by post-MacEtch digital etching. Side-by-side comparison of the midgap interface state density and flat-band capacitance hysteresis of both the unprocessed planar and MacEtched pillar InGaAs metal-oxide-semiconductor capacitors further confirms that the surface of the resultant pillars is as smooth and defect-free as before etching. MacEtch combined with digital etching offers a simple, room-temperature, and low-cost method for the formation of high-quality InGaAs nanostructures that will potentially enable large-volume production of InGaAs-based devices including three-dimensional transistors and high-efficiency infrared photodetectors.

Semiconductor nanowires: to grow or not to grow?

“…Additionally, the presence of sulphur in the S-OA etch was found to have a passivating effect on surface dangling bonds for etched GaAs nanopillars. More recently, metalassisted chemical (wet) etching of InP nanopillars has also been reported to achieve well-controlled anisotropic etching without a measured increase in the density of surface electronic carrier traps [172].…”

Metal‐Assisted Chemical Etching of Silicon in Oxidizing HF Solutions: Origin, Mechanism, Development, and Black Silicon Solar Cell Application

“…Li et al also extended the MacEtch method to other semiconductors such as GaAs and InP. [158][159][160][161] In 1960, Turner [162] proposed that the wet etching of silicon in HF aqueous solution containing oxidants at OCP is an electrochemical process, in which silicon oxidation and dissolution takes place at local anode areas, while the oxidizing agent is reduced at local cathode areas. Turner suggested that an etch pit will form at sites where it is more anodic than cathodic, while a hillock will be produced at areas that are more cathodic than anodic.…”

Hybrid Anodic and Metal‐Assisted Chemical Etching Method Enabling Fabrication of Silicon Carbide Nanowires

“…According to our density function theory calculations, the SBH is about 1.253 eV which is very close to the experimental value, as shown in Figure a,b (Calculation details are shown in the Supporting Information). The barrier will trap the holes generated by the H 2 O 2 reduction (Figure b) although the etching process still hardly occurs as explained above.…”