Cycle-accurate simulation of energy consumption in embedded systems

Simunic, T.; Benini, Luca; Micheli, Giovanni De

doi:10.1109/dac.1999.782199

Cited by 111 publications

(52 citation statements)

References 12 publications

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“…The embedded application is MPEG-layerIII audio decoding. Performance and power were obtained using the simulation tools described in [27], which has been validated against hardware measurements.…”

Section: Resultsmentioning

confidence: 99%

Software-controlled processor speed setting for low-power streaming multimedia

Acquaviva¹,

Benini

Riccò

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we describe a software-controlled approach for adaptively minimizing energy in embedded systems for real-time multimedia processing. Energy is optimized by clock speed setting: the software controller dynamically adjusts processor clock speed to the frame rate (FR) requirements of the incoming multimedia stream. The speed-setting policy is based on a system model that correlates clock speed with best case, average case, and worst case sustainable FRs, accounting for data dependency in multimedia streams. The technique has been implemented in a energy-efficient MPEG3 real-time decoder algorithm designed for wearable devices as a case study. The target system is the Hewlett-Packard SmartBadgeIII prototype system based on the StrongARM1100 processor. Hardware measurements show that computational energy can be drastically reduced (up to 40%) with respect to fixed-frequency operation.

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Section: Resultsmentioning

confidence: 99%

Software-controlled processor speed setting for low-power streaming multimedia

Acquaviva¹,

Benini

Riccò

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

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“…Thus energy is proportional to execution time. This is a reasonable assumption, since studies have shown that the power per instruction remains fairly constant in the absence of non-ideal effects such as pipeline stalls [19].…”

Section: Methodsmentioning

confidence: 99%

“…7: t i,j min < min(R i , R j ). At vertex V i,j , the algorithm iterates through the time window (lines [15][16][17][18][19][20][21]. At each T split , it considers what would happen if task τ i or task τ j were to execute next at each voltage level.…”

Section: Scheduling Algorithmmentioning

confidence: 99%

Reduced energy decoding of MPEG streams

Mesarina

Turner

2003

Multimedia Systems

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Long battery life and high performance multimedia decoding are competing design goals for portable appliances. For a target level of QoS, the achievable battery life can be increased by dynamically adjusting the supply voltage throughout execution. In this paper, an efficient offline scheduling algorithm is proposed for preprocessing stored MPEG audio and video streams. It computes the order and voltage settings at which the appliance's CPU decodes the frames, reducing energy consumption without violating timing or buffering constraints. Our experimental results elucidate the trade-off between QoS and energy consumption. They demonstrate that the scheduler reduces CPU energy consumption by 19%, without any sacrifice of quality, and by nearly 50%, with only slightly reduced quality. The results also evaluate how the QoS/energy trade-off is affected by buffering and processor speed.

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“…The compiler first converts a program into an optimized low level intermediate representation (IR). Then the backend of the compiler generates SystemC TLM/T codes based on performance and energy estimations in the IR [23]. Procedures to generate software TLM/T models with annotations are completely automatic and transparent to the designers.…”

Section: Cache and Memory Simulationmentioning

confidence: 99%

Memory subsystem simulation in software TLM/T models

Cheung

Hsieh

Balarin

2009

2009 Asia and South Pacific Design Automation Conference

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Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the memory subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in systemlevel design space exploration. In this paper, we present a novel technique to simulate memory accesses in software TLM/T models. We use a compiler to automatically expose all memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target memory addresses for accurate cache and memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on memory subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.

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Cycle-accurate simulation of energy consumption in embedded systems

Cited by 111 publications

References 12 publications

Software-controlled processor speed setting for low-power streaming multimedia

Software-controlled processor speed setting for low-power streaming multimedia

Reduced energy decoding of MPEG streams

Memory subsystem simulation in software TLM/T models

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