Custom circuit design as a driver of microprocessor performance

Allen, D.H.; Dhong, S.H.; Hofstee, H. Peter; Leenstra, J.; Nowka, K.; Stasiak, D.; Wendel, D.

doi:10.1147/rd.446.0799

Cited by 32 publications

(21 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In this paper, the architecture design and optimization related to physical implementation is referred to pico-architecture design. Pico-architecture [12] is a kind of organization below the level of micro-architecture, which optimizes the architecture mainly for efficient physical implementation.…”

Section: Pico-architecture Designmentioning

confidence: 99%

Making Effective Decisions in Computer Architects’ Real-World: Lessons and Experiences with Godson-2 Processor Designs

Wang

2008

J. Comput. Sci. Technol.

View full text Add to dashboard Cite

Although the design of many kinds of microprocessors has been under developing for several decades, the computer architecture R&D community lacks well documented lessons and experiences about design decisions in the research literature. In this paper, we systematically present the design decisions we made during the designing and prototyping of Godson-2 series processors. The 250MHz Godson-2B, 450MHz Godson-2C, and 1GHz Godson-2E processors that implement 64-bit, four-issue, out-of-order architecture were taped out in 2003, 2004, and 2005, respectively. Each processor triples its predecessor in the SPEC CPU2000 rates. Our first-hand experiences and lessons gained from these designs would provide unique perspectives and insights that are not available in any existing text books and/or published papers. We summarize 10 critical lessons and experiences based on hundreds of our attempts at architectural and design optimizations for performance improvement of Godson-2 series processors. The issues include silicon-simulation correlation, design balancing, performance optimizing, and pico-architecture tuning. We conclude that persistent improvement, attitude towards work-on-silicon design, and insightful understanding of software and fabrication process are the three most important factors for designing a high performance processor with low energy consumption.

show abstract

Section: Pico-architecture Designmentioning

confidence: 99%

Making Effective Decisions in Computer Architects’ Real-World: Lessons and Experiences with Godson-2 Processor Designs

Wang

2008

J. Comput. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…The performance improvement of microprocessors has been driven traditionally by dynamic logic and microarchitectural improvements [1] and can be further enhanced through circuit design and topology organization. Dynamic logic is an effective logic style in terms of timing and area when compared to its static counterpart due to (1) the absence of requirement for design implementation in complementary PMOS logic, and (2) the use of a clock signal in its implementation of combinational logic circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Dynamic logic has been predominantly used in microprocessors, and their usage has increased the timing performance significantly over static CMOS circuits [1,2]. However, timing optimization of dynamic logic is challenging due to several issues such as charge sharing, noise-immunity, leakage, and environmental and semiconductor process variations.…”

Section: Introductionmentioning

confidence: 99%

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Yelamarthi

Chen

2010

VLSI Design

View full text Add to dashboard Cite

The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixedstatic-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.

show abstract

“…The performance of microprocessors has been driven traditionally by CMOS technology and micro architectural improvements [1]. This performance can be improved to a major extent at the circuit level through design and physical organization.…”

Section: Introductionmentioning

confidence: 99%

Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Yelamarthi

Chen

2007

8th International Symposium on Quality Electronic Design (ISQED'07)

View full text Add to dashboard Cite

Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the Load Balance of Multiple Paths, named LBMP, is proposed. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement. Then by a 64-b adder partitioned to a mixed dynamic-static style, the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6 pJ.

show abstract

Custom circuit design as a driver of microprocessor performance

Cited by 32 publications

References 18 publications

Making Effective Decisions in Computer Architects’ Real-World: Lessons and Experiences with Godson-2 Processor Designs

Making Effective Decisions in Computer Architects’ Real-World: Lessons and Experiences with Godson-2 Processor Designs

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Contact Info

Product

Resources

About