Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Abstract

Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the Load Balance of Multiple Paths, named LBMP, is proposed. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement. Then by a 64-b adder partitioned to a mixed dynamic-static style, the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6 pJ.

Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

“…Fig. 1 depicts a 2-b weighted binary-to-thermometricconverter (WBTC) used in parallel adders [14]. With minimum size transistors in the 2-b WBTC, the worst-case path is path-1.…”

“…A comparison of applying the LBMP algorithm to the 2-b WBTC with and without considering process variation during the timing optimization is shown in the Table 2. Without considering process variation, the 2-b WBTC has delay of 161.37 ps [14]. Considering process variation, the delay was reduced from 161.37 ps to 144 ps.…”

“…A 64-b adder [14] is used as a test case for timing optimization, which is divided into two blocks operating in parallel. Block-1 comprises of a 64-b Carry Convergent Tree (CCT) and a Carry Generator (CG) and block-2 comprises of eight 8-b carry-select adders with four 2-b Thermometric Adders (TA) in each.…”