Current transport of GaAsSb-based DHBTs with different emitter structures

Pan, Chun Ting; Wang, Che Ming; Hsin, Yue-Ming; Zhu, Haoxiang; Kuo, J. M.; Kao, Yung-Chung

doi:10.1016/j.sse.2009.03.013

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…As InGaAs is an alloy, its dielectric constant is calculated using linear interpolation between the corresponding parameters of GaAs and InAs [13,14].The compressive strain developed in In x Ga 1-x As channel grown on InP substrate and InAlAs buffer is considered while calculating band parameters such as band gap and conduction and valence band offsets [12]. In addition, the reported values [15,16,17] of the dielectric constant and the band gap of the substrate InP and buffer material InAlAs are used in our investigation. While simulating CMOS devices at channel lengths 30 nm and 20 nm, the EOT of the devices are chosen 1 nm and 0.8 nm, respectively following the International Technology Roadmap for Semiconductors (ITRS) [18].…”

Section: Device Structure and Simulation Set-upmentioning

confidence: 99%

Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

Tewari

Biswas

Mallik

2014

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking

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MOSFETs based on high mobility channel materials such as Ge for p-MOS devices and InGaAs for n-MOS devices have shown promise for future nanoelectronics. Mobility of carriers can further be improved with the incorporation of barrier layer on top of the channel. We report the impact of barrier layer on the analog performance of hybrid CMOS comprising Ge channel p-MOSFET and InGaAs channel n-MOSFET. Our findings show that the InP barrier thickness of 0.7 nm for InGaAs n-MOSFET and the 0.5 nm thick Si barrier in Ge p-MOSFET exhibit strongest carrier confinement within the respective channel. The gain of hybrid CMOS using such barrier thickness exhibits improvement of 150% and 110% at channel length L g = 30 nm and 20 nm, respectively. Furthermore, our studies reveal that 89.7% and 83% improvement of gain bandwidth product of hybrid CMOS using such barrier thickness at L g = 30 nm and 20 nm, respectively are observed compared with equivalent Si CMOSFETs.

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Section: Device Structure and Simulation Set-upmentioning

confidence: 99%

Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

Tewari

Biswas

Mallik

2014

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking

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“…The intrinsic carrier concentration of 9×10 11 cm -3 for InGaAs [9] has been used in our study. Also the reported values of the dielectric constant and band gap of the barrier materials InP and InAlAs [11] are used in our studies. Earlier experimental findings revealed that the highk/InGaAs interface contained appreciable amount of D it in the range 1×10 12 2 shows a comparison of the simulated device characteristics with the experimental curves as reported in [2] for InGaAs channel n-MOSFETs with different architectures  no barrier, single barrier and double barriers.…”

Section: Introductionmentioning

confidence: 99%

Effects of a Barrier Layer in Ingaas Channel Mosfets for Analog/ Mixed Signal System-on-Chip Applications

Tewari

Biswas

Mallik

2014

IJEEE

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Addition of a barrier layer in an InGaAs MOSFET, which shows promise for high performance logic applications due to enhanced electron mobility, further improves the electron mobility. We report, for the first time, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain, and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance.

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Ultra high-current-gain In<inf>x</inf>Ga<inf>1&#x2212;x</inf>Sb-based DHBT with compositional graded base

Alam

Nayeem

Islam

2012

2012 7th International Conference on Electrical and Computer Engineering

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In x Ga 1-x Sb-based double heterojunction bipolar transistor (DHBT) with compositional graded base and collector is presented. A numerical device simulator Silvaco's ATLAS is used to analyze the performance of the device. The Gummel plots and simulation analysis demonstrate extremely high DC current gain with uniform characteristic for the wide range of collector current. The magnitude of the current gain is found to about 1300 and it is the highest gain for HBTs/DHBTs as reported so far. Preliminarily we achieved this extremely high gain may be due to energy band engineering using compositional gradient technique in the device structure.Index Terms -InGaSb-based DHBT, DC current gain, compositional graded base.

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Current transport of GaAsSb-based DHBTs with different emitter structures

Cited by 5 publications

References 11 publications

Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

Effects of a Barrier Layer in Ingaas Channel Mosfets for Analog/ Mixed Signal System-on-Chip Applications

Ultra high-current-gain In<inf>x</inf>Ga<inf>1&#x2212;x</inf>Sb-based DHBT with compositional graded base

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Current transport of GaAsSb-based DHBTs with different emitter structures

Cited by 5 publications

References 11 publications

Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

Effects of a Barrier Layer in Ingaas Channel Mosfets for Analog/ Mixed Signal System-on-Chip Applications

Ultra high-current-gain In<inf>x</inf>Ga<inf>1&amp;#x2212;x</inf>Sb-based DHBT with compositional graded base

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Ultra high-current-gain In<inf>x</inf>Ga<inf>1−x</inf>Sb-based DHBT with compositional graded base