Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

Abstract

MOSFETs based on high mobility channel materials such as Ge for p-MOS devices and InGaAs for n-MOS devices have shown promise for future nanoelectronics. Mobility of carriers can further be improved with the incorporation of barrier layer on top of the channel. We report the impact of barrier layer on the analog performance of hybrid CMOS comprising Ge channel p-MOSFET and InGaAs channel n-MOSFET. Our findings show that the InP barrier thickness of 0.7 nm for InGaAs n-MOSFET and the 0.5 nm thick Si barrier in Ge p-MOSFET exhibit strongest carrier confinement within the respective channel. The gain of hybrid CMOS using such barrier thickness exhibits improvement of 150% and 110% at channel length L g = 30 nm and 20 nm, respectively. Furthermore, our studies reveal that 89.7% and 83% improvement of gain bandwidth product of hybrid CMOS using such barrier thickness at L g = 30 nm and 20 nm, respectively are observed compared with equivalent Si CMOSFETs.