Current Mask Generation: A Transistor Level Security Against DPA Attacks

Mesquita, Renato C.; Techer,; Торрес,; Sassatelli,; Cambon,; Robert, Michel; Moraes, Fernando

doi:10.1109/sbcci.2005.4286842

Cited by 9 publications

(9 citation statements)

References 16 publications

(18 reference statements)

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“…The first aspect has already been studied earlier, e.g., [18], [19]. In this paper, we are the first to study the second approach under the context of real-time systems.…”

Section: Attacker Modelmentioning

confidence: 89%

Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks

Jiang

Batina

Eles

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Abstract-Embedded systems (ESs) have been a prominent solution for enhancing system performance and reliability in recent years. ESs that are required to ensure functional correctness under timing constraints are referred to as real-time embedded systems (RTESs). With the emerging trend of utilizing RTESs in safety and reliability critical areas, security of RTESs, especially confidentiality of the communication, becomes of great importance. More recently, side-channel attacks (SCAs) posed serious threats to confidentiality protection mechanisms, namely, cryptographic algorithms. In this work, we present the first analytical framework for quantifying the influence of real-time scheduling policies on the robustness of secret keys against differential power analysis (DPA) attacks, one of the most popular type of SCAs. We validated the proposed concept on two representative scheduling algorithms, earliest deadline first scheduling (EDF) and rate-monotonic scheduling (RMS), via extensive experiments.

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“…The first aspect has already been studied earlier, e.g., [18], [19]. In this paper, we are the first to study the second approach under the context of real-time systems.…”

Section: Attacker Modelmentioning

confidence: 89%

Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks

Jiang

Batina

Eles

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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“…The traditional DPA attack relies on this asymmetry and it is expected to remain the major security threat to the standard complementary CMOS logic blocks [2]. In order to tackle the threat of side channel attacks many solutions have been proposed at the architectural level [12][13] [14] [15]. Major attempts have also been made to thwart the DPA threat by removing its root cause.…”

Section: Side Channel and Attacks Methodologiesmentioning

confidence: 99%

Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)

Zadeh

Gebotys

2009

2009 10th International Symposium on Quality of Electronic Design

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This paper investigates the potential security threat to nanoscale Cryptosystem-on-Chip (CoC) posed by the leakage power consumption. The increasing trend of leakage power is shown to be highly correlated with increasing side channel vulnerability. The effect of high threshold voltage (V th ) transistor assignment on improving side channel resistance is analyzed. This investigation shows growth of the leakage mechanisms such as directtunneling and Band-to-Band Tunneling (BTBT) currents may reduce the effectiveness of the high V th transistor assignment technique; however, this technique can still be used in developing side channel resistant cryptosystem. This research is crucial for security sensitive architecture and the results are obtained leading to side channel aware leakage management in design and implementation of CoC in submicron technology.

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“…Some of these techniques try to suppress information leakage through power supply pin by means of: 1) an internally integrated filter [11]; 2) an internal voltage regulator [12], [13]; or 3) a current mask generator to maintain the total current of the circuit constant [14], [15].…”

Section: A State-of-the-artmentioning

confidence: 99%

“…The results which are shown in Figs. [13][14][15] indicate that-using the considered traces-there are potential DPA attacks on all cores. However, the tests based on the Sbox output bits of the protected core of chip 1 do not show a leakage as high as the other tests and the other cores.…”

Section: I(s; L) = H[s] − H[s|l]mentioning

confidence: 99%

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

Gornik

Moradi

Oehm

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Side-channel attacks are one of the major concerns for security-enabled applications as they make use of information leaked by the physical implementation of the underlying cryptographic algorithm. Hence, reducing the side-channel leakage of the circuits realizing the cryptographic primitives is amongst the main goals of circuit designers. In this paper, we present a novel circuit concept, which decouples the main power supply from an internal power supply that is used to drive a single logic gate. The decoupling is done with the help of buffering capacitances integrated into semiconductor. We also introduce-compared to the previously known schemes-an improved decoupling circuit which reduces the crosstalk from the internal to the external power supply. The result of practical side-channel evaluation on a prototype chip fabricated in a 150 nm CMOS technology shows a high potential of our proposed technique to reduce the side-channel leakages.

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Current Mask Generation: A Transistor Level Security Against DPA Attacks

Cited by 9 publications

References 16 publications

Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks

Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks

Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

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