Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)

Abstract

This paper investigates the potential security threat to nanoscale Cryptosystem-on-Chip (CoC) posed by the leakage power consumption. The increasing trend of leakage power is shown to be highly correlated with increasing side channel vulnerability. The effect of high threshold voltage (V th ) transistor assignment on improving side channel resistance is analyzed. This investigation shows growth of the leakage mechanisms such as directtunneling and Band-to-Band Tunneling (BTBT) currents may reduce the effectiveness of the high V th transistor assignment technique; however, this technique can still be used in developing side channel resistant cryptosystem. This research is crucial for security sensitive architecture and the results are obtained leading to side channel aware leakage management in design and implementation of CoC in submicron technology.