HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design

Tanimura, Kazuyuki; Dutt, Nikil

doi:10.1109/les.2012.2193115

Cited by 11 publications

(9 citation statements)

References 21 publications

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“…This is because it is equivalent to removing the irrelevant datapath element in SCA to reduce the noise level when recovering a particular key-byte. The crucial non-linear component S-Box and the downstream logic for key-related operations are all preserved, which is the target of most SCA attacks [14]. The methodology can also be readily applied to any other cipher.…”

Section: Simulation Resultsmentioning

confidence: 99%

Role of power grid in side channel attack and power-grid-aware secure design

Wang

Yueh

Roy

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Side-channel attack (SCA) is a method in which an attacker aims at extracting secret information from crypto chips by analyzing physical parameters (e.g. power). SCA has emerged as a serious threat to many mathematically unbreakable cryptography systems. From an attacker's point of view, the difficulty of mounting SCA largely depends on Signal-to-Noise Ratio (SNR) of the side-channel information. It has been shown that SNR primarily depends on algorithmic and circuit-level implementation, measurement noise, as well as device thermal noise. However, to the best of our knowledge, there has not been any study on the effect of power delivery network (PDN) on SCA resistance. We note that the PDN plays a significant role in SNR of measured supply current. Furthermore, SCA resistance strongly depends on the operating frequency due to RLC structure of a power grid. In this paper, we analyze the effect of power grid on SCA and provide quantitative results to demonstrate the frequency-dependent SCA resistance due to PDN-induced noise. This property can potentially be exploited by an attacker to facilitate the attack by operating a device at favorable frequency points. On the other hand, from a designer's perspective, one can explore countermeasures to secure the device at all operating frequencies while minimizing the design overhead. Based on this observation, we propose a frequency-dependent noise-injection based compensation technique to efficiently protect against SCA. Simulation results using realistic PDN model as well as experimental measurements using FPGA test board validate the observations on role of PDN in SCA and the efficacy of the proposed compensation approach.

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Section: Simulation Resultsmentioning

confidence: 99%

Role of power grid in side channel attack and power-grid-aware secure design

Wang

Yueh

Roy

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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“…The Fig. 8 Single-to-alternating spacer converter [48] other data path is used to generate the complementary output. However, the complementary output is generated using the inverted output of the product term segment from the true data path.…”

Section: Reduced Complementary Dynamic and Differential Logic (Rcddl)mentioning

confidence: 99%

“…The HDRL style [48] is designed based on the observations of the ground voltage (VSS) current instead of the usual supply voltage (VDD) current of the circuit. The hypothesis used is that the VSS current drawn by a cell is indistinguishable for different inputs.…”

Section: Homogeneous Dual-rail Logic (Hdrl)mentioning

confidence: 99%

“…Another concern of such logic style is the fact that all the assumptions are made based on observing the VSS current without taking into consideration the source current that is drawn by the circuit. Results shown in [48] are based on simulation tools; further practical experiments on silicon is necessary to back up the assertions made regarding the HDRL logic style.…”

Section: Homogeneous Dual-rail Logic (Hdrl)mentioning

confidence: 99%

“…11 BCDL cell of the two-input OR gate [46] Fig. 12 HDRL AND gate [48] and logically AND-ed with the pre-charge signal, which is usually generated by the system clock. The output of the AND gate is connected to the LUT as a pre-charge absorbed input.…”

Section: Pre-charge Absorbed Dplmentioning

confidence: 99%

See 2 more Smart Citations

Review of gate‐level differential power analysis and fault analysis countermeasures

Marzouqi¹,

Al‐Qutayri²,

Salah³

2014

IET Information Security

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A machine learning low‐dropout regulator‐assisted differential power analysis attack countermeasure with voltage scaling

Cheng

Liu

Sun

et al. 2023

Circuit Theory & Apps

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Summary False key‐controlled aggressive voltage scaling (FKCAVS) technique is a lightweight and effective leakage power analysis (LPA) attack countermeasure. However, the regular FKCAVS technique may not be utilized as a countermeasure against differential power analysis (DPA) attacks unconditionally. The primary reason is that the working frequency of DPA attacks is significantly higher than the corresponding frequency of LPA attacks. Thus, it is difficult to make the speed of voltage scaling keep pace with the speed of DPA attacks by employing the regular FKCAVS technique. In this paper, a fast FKCAVS technique is proposed to maximize the security of a cryptographic circuit (CC) against DPA attacks while minimizing the corresponding overhead by embedding a machine learning low‐dropout (LDO) regulator (MLLR). As shown in the result, by deploying the proposed FKCAVS technique, the measurement‐to‐disclose (MTD) value against DPA attacks is maintained over 1 million with less than 17.4% power/area overhead.

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HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design

Cited by 11 publications

References 21 publications

Role of power grid in side channel attack and power-grid-aware secure design

Role of power grid in side channel attack and power-grid-aware secure design

Review of gate‐level differential power analysis and fault analysis countermeasures

A machine learning low‐dropout regulator‐assisted differential power analysis attack countermeasure with voltage scaling

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