Role of power grid in side channel attack and power-grid-aware secure design

Wang, Xinmu; Yueh, Wen; Roy, Debapriya Basu; Narasimhan, Seetharam; Zheng, Yu; Mukhopadhyay, Saibal; Mukhopadhyay, Debdeep; Bhunia, Swarup

doi:10.1145/2463209.2488830

Cited by 39 publications

(10 citation statements)

References 18 publications

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“…Wang et al studied the design of power grids to deter power attacks [Wan13]. They showed that the current pattern generated by a circuit is filtered by the PDN before it can be observed at the pins making the 'logical' and 'physical' current patterns different.…”

Section: Previous Workmentioning

confidence: 99%

Information theoretic models for signatures in VLSI power delivery systems

Wolf

Mukhopodhyay

2014

Proceedings of the 9th Workshop on Embedded Systems Security

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We propose several abstract models for power distribution systems (PDSs) and show how the physics of PDNs pose limits on our ability to protect against power attacks. Integrated circuits increasingly use integrated voltage regulators (IVRs) to condition the on-chip power signal. IVRs present new opportunities for both decreasing observability of logic activity (power attacks) and monitoring the details of logic activity (Trojan horse detection). We propose three different models for the information in regulated power signals. Longer regulation periods improve the regulator's ability to hide information about the behavior of the logic; unfortunately, longer regulation periods may result in poorer power quality or larger regulator area.Power attack, power delivery network, integrated voltage regulator. KeywordsPower attack, power signature, Trojan horse detection, power delivery network, integrated voltage regulator.

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Section: Previous Workmentioning

confidence: 99%

Information theoretic models for signatures in VLSI power delivery systems

Wolf

Mukhopodhyay

2014

Proceedings of the 9th Workshop on Embedded Systems Security

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“…In particular, power dissipation and electromagnetic (EM) emissions from modern SoCs can leak compromising information and has emerged as key threats to security of modern SoCs. Consequently, power and EM side channel attack on AES architectures have received signifcant attention over last decade [2], [7]- [11]. Although majority of the works focus on inhibiting power attacks, preventing EM attacks is gaining more importance in the era of mobile and ubiquituous computing, due to the simplicity and inexpensive nature of the EM attack.…”

Section: Introductionmentioning

confidence: 99%

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

Kar

Singh

Mathew

et al. 2018

IEEE J. Solid-State Circuits

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Modern high-performance as well as powerconstrained System-on-Chips (SoC) are increasingly using hardware accelerated encryption engines to secure computation, memory access, and communication operations. The electromagnetic (EM) emission from a chip leaks information of the underlying logical operation being performed by the chip. As the EM information leakage can be collected using low-cost instruments and non-invasive measurements, EM based sidechannel attacks (EMSCA) have emerged as a major threat to security of encryption engines in a SoC. This paper presents the concept of Blindsight where an high-frequency inductive voltage regulator integrated on the same chip with an encryption engine is used to increase resistance against EMSCA. High-frequency (∼100MHz) inductive integrated voltage regulators (IVR) are present in modern microprocessors to improve energy-efficiency. We show that an IVR with a randomized control loop (R-IVR) can reduce EMSCA as the integrated inductance acts as a strong EM emitter and blinds an adversary from EM emission of the encryption engine. The measurements are performed on a prototype circuit board with a test-chip containing two architectures of a 128-bit Advanced Encryption Standard (AES) engine powered by a high-frequency (125MHz) R-IVR with wirebond inductor. The EM measurements are performed under two attack scenarios, one, where an adversary gains complete physical access of the target device (EMSCA with Physical Access) and the other, where the adversary is only in proximity of the device (Proximity EMSCA). The resistance to EMSCA is characterized considering a naive adversary as well as a skilled one with intelligent post-processing capabilities. In both attack modes, for a naive adversary, EM emission from a baseline IVR (B-IVR, without control loop randomization) increases EMSCA resistance compared to a standalone AES engine. However, a skilled adversary with intelligent post-processing can observe information leakage in Test Vector Leakage Assessment (TVLA) test. Subsequently, we show that EM emission from the R-IVR blinds the attacker and significantly reduces SCA vulnerability of the AES engine. A range of practical side-channel analysis including TVLA, Correlation Electromagnetic Analysis (CEMA), and a template based CEMA shows that R-IVR can reduce information leakage and prevent key extraction even against a skilled adversary.

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“…Placement performance largely impacts the downstream stages of power grid design [Wang et al 2013], clock tree synthesis [Lu et al 2012a], power optimization [Lu et al 2012b], global detail routing [Lu and Sham 2013], postlayout simulation [He et al 2012], and design variability [Zheng et al 2014]. As the technology node enters the deep nanometer scale [ITRS 2011] with billion-transistor integration, the performance of the placement engine becomes dominant on the overall quality of the design.…”

Section: Introductionmentioning

confidence: 99%

ePlace

Chen

Chang

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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We develop a flat, analytic, and nonlinear placement algorithm, ePlace, which is more effective, generalized, simpler, and faster than previous works. Based on the analogy between placement instance and electrostatic system, we develop a novel placement density function eDensity, which models every object as positive charge and the density cost as the potential energy of the electrostatic system. The electric potential and field distribution are coupled with density using a well-defined Poisson's equation, which is numerically solved by spectral methods based on fast Fourier transform (FFT). Instead of using the conjugate gradient (CG) nonlinear solver in previous placers, we propose to use Nesterov's method which achieves faster convergence. The efficiency bottleneck on line search is resolved by predicting the steplength using a closed-form equation of Lipschitz constant. The placement performance is validated through experiments on the ISPD 2005 and ISPD 2006 benchmark suites, where ePlace outperforms all state-of-the-art placers (Capo10.5, FastPlace3.0, RQL, MAPLE, ComPLx, BonnPlace, POLAR, APlace3, NTUPlace3, mPL6) with much shorter wirelength and shorter or comparable runtime. On average, of all the ISPD 2005 benchmarks, ePlace outperforms the leading placer BonnPlace with 2.83% shorter wirelength and runs 3.05× faster; and on average, of all the ISPD 2006 benchmarks, ePlace outperforms the leading placer MAPLE with 4.59% shorter wirelength and runs 2.84× faster. . 2015. ePlace: Electrostatics-based placement using fast fourier transform and nesterov's method.

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Role of power grid in side channel attack and power-grid-aware secure design

Cited by 39 publications

References 18 publications

Information theoretic models for signatures in VLSI power delivery systems

Information theoretic models for signatures in VLSI power delivery systems

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

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