2010
DOI: 10.1063/1.3529492
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Cu penetration into low-k dielectric during deposition and bias-temperature stress

Abstract: Cu penetration into low-k dielectrics can cause serious reliability issues in on-chip interconnect systems. Using secondary ion mass spectrometry with both front-side and back-side depth profiling strategies, Cu was found to diffuse into SiCOH low-k dielectric in a Cu/SiCOH/Si capacitor during Cu deposition. After bias-temperature stressing the capacitor at 270 °C and 2.5 MV/cm, Cu penetrates further into SiCOH, but its distribution profile is the same as that after the same temperature annealing without elect… Show more

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Cited by 23 publications
(13 citation statements)
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“…We also note that Cu profiles under BTS/TS in either as-deposited or VUV-irradiated SiCOH come with "humps" at shallow depth. These humps have been previously observed by He et al 10 and are believed to be related to Cu diffusion kinetics and solubility in SiCOH. Future work is planned to clarify the impact of VUV irradiation on Cu diffusion kinetics and solubility in SiCOH.…”
Section: -supporting
confidence: 68%
See 1 more Smart Citation
“…We also note that Cu profiles under BTS/TS in either as-deposited or VUV-irradiated SiCOH come with "humps" at shallow depth. These humps have been previously observed by He et al 10 and are believed to be related to Cu diffusion kinetics and solubility in SiCOH. Future work is planned to clarify the impact of VUV irradiation on Cu diffusion kinetics and solubility in SiCOH.…”
Section: -supporting
confidence: 68%
“…Instead of depositing Cu electrodes on the surface of low-k SiCOH thin films, the sample preparation procedure is optimized by employing PECVD deposition of SiCOH on polished Cu thin-film substrates, because Cu was found to diffuse into the dielectric layer during depositing Cu electrodes onto the SiCOH using either e-beam evaporation or sputter deposition. 10 FIG. 1.…”
Section: Effects Of Vacuum-ultraviolet Irradiation On Copper Penetratmentioning
confidence: 99%
“…247 Integrated requirements.-Cu/metal diffusion resistance.-An obvious integrated requirement for any dielectric diffusion barrier / metal capping layer is to prevent diffusion of the metal wire into the surrounding ILD. The presence of metal contamination in the ILD has been attributed to a number of reliability issues 248 such as increased leakage currents, [249][250][251] decreased TDDB lifetime [252][253][254][255][256][257][258] and shifts in CMOS device performance. [259][260][261][262][263][264] A number of Cu barrier performance tests have been reported in the literature.…”
Section: -122mentioning
confidence: 99%
“…However, such method 8 usually implies a complete consumption of the metal catalyst, incurring higher cost for producing graphene. Furthermore, chemical etching generates the large quantity of chemical wastes which require vigilant disposal because the metal residues coming either from catalyst or from the etchant, even in very small amount under the form of trace, severely alter the electronic, optical and mechanical properties of the graphene material [45,46]. Hence the exploration on the graphene transfer methods which could preserve the perfectness of the surface of catalyst foil but without deterioration of the crystallinity of graphene is important and it represents the major branch of graphene research area right now.…”
Section: Influence Of the Substrate On The Graphene Propertiesmentioning
confidence: 99%