Effects of vacuum-ultraviolet irradiation on copper penetration into low-k dielectrics under bias-temperature stress

Abstract

The effects of vacuum-ultraviolet (VUV) irradiation on copper penetration into non-porous low-k dielectrics under bias-temperature stress (BTS) were investigated. By employing x-ray photoelectron spectroscopy depth-profile measurements on both as-deposited and VUV-irradiated SiCOH/ Cu stacks, it was found that under the same BTS conditions, the diffusion depth of Cu into the VUV-irradiated SiCOH is higher than that of as-deposited SiCOH. On the other hand, under the same temperature-annealing stress (TS) without electric bias, the Cu distribution profiles in the VUV-irradiated SiCOH were same with that for the as-deposited SiCOH. The experiments suggest that in as-deposited SiCOH, the diffused Cu exists primarily in the atomic state, while in VUV-irradiated SiCOH, the diffused Cu is oxidized by the hydroxyl ions (OH À) generated from VUV irradiation and exists in the ionic state. The mechanisms for metal diffusion and ion injection in VUV irradiated low-k dielectrics are discussed. V

Defect-induced bandgap narrowing in low-k dielectrics

“…[1][2][3] These reliability issues are typically attributed to the presence and creation of electrical "traps" or "defects" from porogen removal and plasma-etching processes that expose the material to intense ultraviolet (UV) and vacuum UV (VUV) photons, energetic ions, and chemically active radicals. [4][5][6][7] Numerous electrically based measurements have shown a direct correlation between trap/defect states, leakage current, breakdown voltages, and TDDB failures of low-k materials. 3,8,9 In most cases, the conduction mechanisms in dielectric materials are fundamentally dependent on accurate knowledge of the depths and locations of trap states within the bandgap.…”

Evidence of Mixed Oxide Formation on the Cu/SiO2 Interface

“…Moreover, the continuous downscaling of complementary metal oxide semiconductor (CMOS) devices and interconnections is limited by the need of layers thick enough to be continuous so as to provide robust performance. In this sense, several groups are working in the study of copper penetration into low- k dielectrics such as SiCOH or doped Si. , Most of them are interested in the failure of SiO 2 as an insulating dielectric due to the penetration of Cu by measuring time dependent dielectric breakdowns, I – V curves, or C – V curves, although several works report on Cu + diffusion by XPS. , Nevertheless, only a few publications are centered in understanding the problem of interface diffusion.…”

“…16,17 Most of them are interested in the failure of SiO 2 as an insulating dielectric due to the penetration of Cu by measuring time dependent dielectric breakdowns, I−V curves, or C−V curves, although several works report on Cu + diffusion by XPS. 18,19 Nevertheless, only a few publications are centered in understanding the problem of interface diffusion.…”

Measurements of Schottky barrier at the low-k SiOC:H/Cu interface using vacuum ultraviolet photoemission spectroscopy

“…1 Continuous technology scaling may eventually make the barrier layers so thin that the Cu lines are in direct contact with the low-k dielectrics. 4 However, the reduced-k-value of interlayer dielectrics, typically produced with the introduction of nanoporosities, can seriously compromise the performance of an actual low-k/ Cu interconnect. [5][6][7] One critical challenge is electrical leakage at the interface between Cu and low-k dielectrics, particularly as electric fields approach 1 MV/cm or greater for <10-nm technology nodes.…”

“…The details of the deposition process and the a-SiOC:H film have been previously reported in detail. 4,11 In brief, the Cu thin films utilized for these experiments consist of electrochemically plated (ECP) Cu that is chemically mechanically polished (CMP) using a Cu ECP and CMP process optimized for 32-nm interconnect technologies. The ECP Cu was plated on a Cu seed and a TaN adhesion layer sputter deposited on 300-mm diameter Si (001) substrates on which 100 nm of thermal oxide had been previously grown.…”