Crosstalk Induced Performance Analysis of Single Wall Carbon Nanotube Interconnects Using Stable Finite-Difference Time-Domain Model

Venkataiah, C.; Satyaprasad, K.; Prasad, T. Jayachandra

doi:10.1166/jno.2018.2300

Cited by 6 publications

(7 citation statements)

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“…Because of the high mobility of electrons movement near ballistic transport and high driving capacity and smaller area, the CNTFETs are become promising alternate for CMOS technology especially when the device scaled at nanometer range. The authors [21][22][23][24][25][26] revealed that CNTFET outperforms compared to CMOS for both circuits and transmission lines. The positive feedback logic shown superior performance in the design of BCAM cells and other circuits needed to realize the BCAM array such as priority encoder, decoder and other logic gates [27,28].…”

Section: Fig1 General 4x4 Bcam Arraymentioning

confidence: 99%

Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

Gangadhar*,

Babulu

2019

IJEAT

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In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4x4 CNTFET BCAM array are in the range of micro watt (µW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.

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Section: Fig1 General 4x4 Bcam Arraymentioning

confidence: 99%

Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

Gangadhar*,

Babulu

2019

IJEAT

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“…Hence, increasing the amount of power dissipation in integrated circuits. Improvement in technology or scaling leads to provide a significant increase in parasitic interconnects wires [6][7][8][9][10][11][12]. The inductive effect and capacitive coupling effect give interconnect wire coupling crosstalk significance and cause many signal integrity problems.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

Venkataiah¹,

Setty²,

Ramanjaneyulu³

et al. 2023

International Journal of Emerging Research in Engineering, Science, and Management

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As technology extended from deep sub-micron technology to nanometer regimes, the conventional copper (Cu) wire will not be able to continue. Now a substitute approaches such as Carbon Nano Tube (CNT) interconnects have been suggested to ignore the problems associated with global interconnects. Hence in this work, crosstalk analysis of Complementary metal oxide semiconductor (CMOS) buffer-driven of different interconnects have been analyzed for peak overshoot and overshoot width of Cu and CNTs for 16nm technology. For analyzing peak overshoot, the interconnect lengths are varied from 100um to 500um in 16 technology node for Cu, single walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). The values of the peak overshoot and overshoot width changes, as the interconnect length increases, the peak overshoot and width is going to be increases. As Compared to Cu, SWCNT and MWCNT, the peak overshoot and width for SWCNT is lesser than copper and MWCNT. The MWCNT interconnect is less than that of conventional Copper interconnects.

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“…Hence, increasing the amount of power dissipation integrated circuits. As improvement in technology or scaling will leads to have also provides in a significant may increase in parasitic in interconnects wires [6][7][8][9][10][11][12]. Inductive effect and capacitive coupling effect gives interconnect wire coupling crosstalk significant and cause many signal integrity problems.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Analysis of On-chip VLSI Interconnects

Jayamma¹,

Ramanjaneyulu²,

Sathish³

et al. 2022

International Journal of Emerging Research in Engineering, Science, and Management

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In this paper dynamic crosstalk is analyzed for coupled on-chip VLSI interconnects in different conditions. The proposed work has taken the MOS transistor analytical expressions. In this work, calculated the transition delays and different timings of the interconnect aggressor and interconnect victim drivers for in-phase switching and out-of-phase switching. All the calculated results are compared with simulations in SPICE. The average error in the transmission delay using SPICE is 2.02 and 3.274% for the interconnect aggressor and interconnect victim buffers for in phase switching, respectively. The average errors in the same are 2.3 and 1.87% for out phase switching event.

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Crosstalk Induced Performance Analysis of Single Wall Carbon Nanotube Interconnects Using Stable Finite-Difference Time-Domain Model

Cited by 6 publications

References 0 publications

Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

Crosstalk Analysis of On-chip VLSI Interconnects

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