Cross-sectional transmission electron microscopy investigation of Ti/Si reaction on phosphorus-doped polycrystalline silicon gate

Abstract

Titanium interaction with phosphorus-doped polycrystalline silicon gate electrodes was investigated by cross-sectional transmission electron microscopy and correlated with sheet resistance measurements. Phosphorus concentration above 1×1016 ion/cm2 in the polycrystalline silicon leads to decreased TiSi2 formation, discontinuous metal silicide layer, and increased sheet resistance. A possible cause could be the formation of titanium phosphide at high phosphorus concentration in the polycrystalline silicon, competing with the total titanium available for silicide formation.

Substrate Influence on the Formation of Titanium Silicide on Polycrystalline Silicon

“…(3) polycrystalline silicon, with the same deposition parameters as (2), except that nominally undoped. (2) polycrystalline silicon, 500 nm thick, LPCVD deposited on 25 nm of silicon dioxide, and phosphorous doped.…”

Enhanced formation of low-resistivity TiSi2 contacts for deep submicron devices

“…For self-aligned silicidation process silicides are formed on source, drain and gate regions simultaneously to ease the lithography requirements and to lower the contact resistance. Low-resistivity C54-TiSi 2 is currently the most widely used silicide for the self-aligned technology of ultralarge scale integrated circuits because it possesses the lowest resistivity among all silicides, low contact resistance, and good thermal properties as well as compatibility with the self-aligned silicidation (SALICIDE) process (Wong et al 1983(Wong et al , 1986). However it has been found that as the integrated circuit device dimensions scale down to deep submicron region, the high-resistivity C49-to C54-TiSi 2 conversion becomes increasingly difficult; this is attributed to the low density of nucleation sites for the C54-TiSi 2 phase (Lasky et al 1991).…”