CoWare-a design environment for heterogeneous hardware/software systems

Rompaey, K. Van; Verkest, D.; Bolsens, I.; Man, H. De

doi:10.1109/eurdac.1996.558213

Cited by 52 publications

(27 citation statements)

References 8 publications

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“…The language-based approach is the state of the art that is reflected in tools such as CoWare [8] which uses a clientserver approach to communication or AREXSYS [9] which uses a remote procedure call protocol. These EDA systems provide libraries with communication primitives implementing the backbone protocol.…”

Section: IIImentioning

confidence: 99%

Embedded system design with multiple languages

Ernst

Jerraya²

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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Section: IIImentioning

confidence: 99%

Embedded system design with multiple languages

Ernst

Jerraya²

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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“…Furthermore, TLM proposals so far focus on simulation only and they lack the path to vertical integration of models for implementation and synthesis. There are several approaches dealing with automatic generation, synthesis and refinement of communication [3,7]. None of these approaches, however, provide intermediate models breaking the design gap into smaller steps required for rapid, early exploration of critical design issues.…”

Section: B Related Workmentioning

confidence: 99%

System-level communication modeling for network-on-chip synthesis

Gerstlauer

Shin

Dömer

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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Abstract-As we are entering the network-on-chip era and system communication is becoming a dominating factor, communication abstraction and synthesis are becoming the integral part of system design flows. The key to the success of any design flow are well-defined abstraction levels and models, which enable automation of early validation, synthesis and verification. In this paper, we define system communication abstraction layers and corresponding design models that support successive, stepwise refinement from abstract message-passing down to a cycleaccurate, bus-functional implementation. Experimental results show the benefits of our definitions and design flow. I. INTRODUCTIONAs SoCs grow in complexity and size, on-chip communication is becoming increasingly important. Furthermore, new classes of optimization problems arise as communication delays and latencies across the chip start dominating computation delays. In other words, simple (e.g. bus based) communication architectures are not sufficient any more. Therefore, as we enter the network-on-chip (NoC) era, new network-based communication architectures and design flows are needed.Communication design for SoCs poses unique challenges in order to cover a wide range of architectures while at the same time offering new opportunities for optimizations based on the application-specific nature of system designs. The goal is therefore, to develop a corresponding NoC communication design flow that enables rapid design space exploration through design automation in order to achieve the required productivity gains while supporting a wide range of implementations.In order to automate the NoC design process, a well-defined design flow with clear and unambiguous abstraction levels, models, and transformations is required. The key to the success of this approach are properly defined design models. Arbitrary models without clear semantics do not enable synthesis and verification. For example, only subsets of hardware description languages such as VHDL or Verilog are synthesizable or verifiable. In addition, synthesis requires clear definitions of the target architecture and the set of synthesis steps to transform the input model into the target model.In this work, we aim to define such models, design steps, and corresponding model transformations that are necessary for an automated network-on-chip design flow. Note that due to space limitations, this paper can only provide an overview of the approach. Details can be found in [8].

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“…Several approaches deal with automatic generation and synthesis of communication [5], [6]. None of these, however, provides intermediate models that break the design task into smaller steps required for early exploration.…”

Section: Related Workmentioning

confidence: 99%

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

Gerstlauer¹,

Shin²,

Peng³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With growing market pressures and rising system complexities, automated system-level communication design with efficient design space exploration capabilities is becoming increasingly important. At the same time, customized network-oriented communication architectures become necessary in enabling a high-performance communication among the system components. To this end, corresponding communication design flows that are supported by efficient design automation techniques need to be developed. In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures. Our approach supports a two-stage design flow using automated model refinement toward custom heterogeneous communication networks. Starting from an abstract specification of the desired communication channels, our environment automatically generates tailored network models at various levels of abstraction. At its core, an automatic layer-based refinement approach is utilized. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Our experimental results show significant productivity gains over a traditional communication design, allowing early and rapid design space exploration.Index Terms-Communication synthesis, embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), systemlevel design, transaction-level modeling (TLM).

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CoWare-a design environment for heterogeneous hardware/software systems

Cited by 52 publications

References 8 publications

Embedded system design with multiple languages

Embedded system design with multiple languages

System-level communication modeling for network-on-chip synthesis

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

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