Abstract-As we are entering the network-on-chip era and system communication is becoming a dominating factor, communication abstraction and synthesis are becoming the integral part of system design flows. The key to the success of any design flow are well-defined abstraction levels and models, which enable automation of early validation, synthesis and verification. In this paper, we define system communication abstraction layers and corresponding design models that support successive, stepwise refinement from abstract message-passing down to a cycleaccurate, bus-functional implementation. Experimental results show the benefits of our definitions and design flow.
I. INTRODUCTIONAs SoCs grow in complexity and size, on-chip communication is becoming increasingly important. Furthermore, new classes of optimization problems arise as communication delays and latencies across the chip start dominating computation delays. In other words, simple (e.g. bus based) communication architectures are not sufficient any more. Therefore, as we enter the network-on-chip (NoC) era, new network-based communication architectures and design flows are needed.Communication design for SoCs poses unique challenges in order to cover a wide range of architectures while at the same time offering new opportunities for optimizations based on the application-specific nature of system designs. The goal is therefore, to develop a corresponding NoC communication design flow that enables rapid design space exploration through design automation in order to achieve the required productivity gains while supporting a wide range of implementations.In order to automate the NoC design process, a well-defined design flow with clear and unambiguous abstraction levels, models, and transformations is required. The key to the success of this approach are properly defined design models. Arbitrary models without clear semantics do not enable synthesis and verification. For example, only subsets of hardware description languages such as VHDL or Verilog are synthesizable or verifiable. In addition, synthesis requires clear definitions of the target architecture and the set of synthesis steps to transform the input model into the target model.In this work, we aim to define such models, design steps, and corresponding model transformations that are necessary for an automated network-on-chip design flow. Note that due to space limitations, this paper can only provide an overview of the approach. Details can be found in [8].