System-level communication modeling for network-on-chip synthesis

Abstract

Abstract-As we are entering the network-on-chip era and system communication is becoming a dominating factor, communication abstraction and synthesis are becoming the integral part of system design flows. The key to the success of any design flow are well-defined abstraction levels and models, which enable automation of early validation, synthesis and verification. In this paper, we define system communication abstraction layers and corresponding design models that support successive, stepwise refinement from abstract message-passing down to a cycleaccurate, bus-functional implementation. Experimental results show the benefits of our definitions and design flow. I. INTRODUCTIONAs SoCs grow in complexity and size, on-chip communication is becoming increasingly important. Furthermore, new classes of optimization problems arise as communication delays and latencies across the chip start dominating computation delays. In other words, simple (e.g. bus based) communication architectures are not sufficient any more. Therefore, as we enter the network-on-chip (NoC) era, new network-based communication architectures and design flows are needed.Communication design for SoCs poses unique challenges in order to cover a wide range of architectures while at the same time offering new opportunities for optimizations based on the application-specific nature of system designs. The goal is therefore, to develop a corresponding NoC communication design flow that enables rapid design space exploration through design automation in order to achieve the required productivity gains while supporting a wide range of implementations.In order to automate the NoC design process, a well-defined design flow with clear and unambiguous abstraction levels, models, and transformations is required. The key to the success of this approach are properly defined design models. Arbitrary models without clear semantics do not enable synthesis and verification. For example, only subsets of hardware description languages such as VHDL or Verilog are synthesizable or verifiable. In addition, synthesis requires clear definitions of the target architecture and the set of synthesis steps to transform the input model into the target model.In this work, we aim to define such models, design steps, and corresponding model transformations that are necessary for an automated network-on-chip design flow. Note that due to space limitations, this paper can only provide an overview of the approach. Details can be found in [8].

Mixture models for system-level communication analysis at higher levels of abstraction

“…The communication resources are further abstracted through the use of communication layers based on the OSI model. This layering approach to communication architecture abstraction has been adopted by others [4], [17], [18]. A similar approach is found in [5], where a C++ library is introduced to facilitate the modeling of layered interconnection networks.…”

Host-compiled simulation of multi-core platforms

“…TLM allows orders of magnitude faster simulations by abstracting away pin-and wire-level protocol details into an interface at the level of bus read/write transactions [11], [12], [13], [14] (protocol TLM, P-TLM) or complete data packets (network TLM, N-TLM) [15], [16]. Internally, bus TLM descriptions realize an abstracted, yet accurate model of the functionality and timing of such bus transactions.…”

System-Level Middleware for Embedded Hardware and Software Communication

“…Orthogonalization of concerns in system-level design as proposed by [2], and more recently by [3] and [4], provide an object model similar to what this paper assumes, but most actual implementations focus on a structural view of the system and do not care about location transparency. In [5] a uniform communication mechanism for HW and SW resources is proposed, based on a central HW-SW OS and a HW abstraction layer to provide task abstractions for HW components.…”