Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

Abstract

Abstract-With growing market pressures and rising system complexities, automated system-level communication design with efficient design space exploration capabilities is becoming increasingly important. At the same time, customized network-oriented communication architectures become necessary in enabling a high-performance communication among the system components. To this end, corresponding communication design flows that are supported by efficient design automation techniques need to be developed. In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures. Our approach supports a two-stage design flow using automated model refinement toward custom heterogeneous communication networks. Starting from an abstract specification of the desired communication channels, our environment automatically generates tailored network models at various levels of abstraction. At its core, an automatic layer-based refinement approach is utilized. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Our experimental results show significant productivity gains over a traditional communication design, allowing early and rapid design space exploration.Index Terms-Communication synthesis, embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), systemlevel design, transaction-level modeling (TLM).

Automatic generation of transducer models for multicore system design

“…These considerations are put in place to simplify the design of the transducer hardware and they do not in any way restrict the communication models used at the application level. Channels with complex data types or other communication mechanisms, such as non-blocking FIFO, handshake, priority queues and so on, can easily be built on top of blocking FIFOs in a layered fashion [16]. The higher layers implementing the complex channels on top of type-less blocking FIFOs can be implemented in software.…”

Hardware-dependent Software synthesis for many-core embedded systems

“…POLIS [7] (Co-Design Finite State Machine), DESCARTES [19] (ADF and an extended SDF), Cortadella [8] (petri nets) and SCE [10] (SpecC) provide some automation for SW generation from certain languages and models of computation. Our approach, in ESE, provides a C based input with multi-core support and has been demonstrated with actual board implementation.…”

Automatic generation of hardware dependent software for MPSoCs from abstract system specifications

“…The SW application executes on an off-the-shelf RTOS or by using an interrupt driven system for small applications. The generation of the TLM has been described in [11]. This paper focuses on SW synthesis from the generated TLM.…”

“…Then, the user can explore the design space by entering architecture decisions into the design flow. The flow automatically generates a TLM that reflects the designers choices [11]. The generated TLM allows for a fast and accurate validation, performance evaluation, prototyping, and debugging of the complete system.…”