For low k1 lithography process, some minor facotrs' impacts are strongly enhanced such as MEEF, lens distortion, wafer topography, pattern density and so on. How to minimize those impacts becomes more and more important. Unfortunately those impacts are not controlled by lithography process itself and caused by other modules such as layout design, integration schemes, mask making, film deposition, CMP and so on. A method to reduce those impacts is quietly needed. DFM (Design for Manufacturability) is a popular and effective approach to get more robust process by reducing pattern loading effect. In this paper, we will show our study on wafer local topography in low k1 lithography process. Products with sub-90nm design rules and different device structures are processed by pure KrF process. The maximum 0.82NA KrF scanner tools are used. The k1 factor is low enough to enhance the impacts. By using DFM solutions, we had resolved these issues and the process window are obviously improved.