Cost benefits for the application of COTS ATE

Ambler, T.; Schuhmacher, C.

doi:10.1109/autest.1999.800412

Cited by 2 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Consider the military, with smaller volumes of higher-complexity items but an urgent requirement for maintainability. 3 Test must economically span both extremes.…”

Section: Test Costmentioning

confidence: 99%

Economics of built-in self-test

Ungar

Ambler

2001

IEEE Des. Test. Comput.

Self Cite

View full text Add to dashboard Cite

costs and few benefits. The truth lies somewhere in between these two extremes. The ideal solution is a sound economic model that lets designers-who have products with various production volumes, design complexities, specifications, support requirements, and customer stress levels-better determine what type of BIST, if any, is best for their applications.IC manufacturers evaluate the benefits and costs of wafer-, intellectual-property-, system-ona-chip-, and IC-level BISTs based on profit margin impact. Board manufacturers typically focus on the economics of boundary scan and boardlevel BIST implementations, although they should also consider the benefits derived from IC-level BIST. Board-level BIST, a relatively new phenomenon, 1 integrates IC-level, boundary scan, and board-level logic BIST for both circuit card vendors and system integrators. System manufacturers consider system-, board-, and IClevel BIST in determining the economics of the Economics of Built-in Self-Test International Test Conference 70 Using built-in self-test at the right level offers users significant cost savings, but determining which level, if any, is best for BIST can be complex. A detailed economic analysis can unravel heterogeneous costs and benefits so that designers and managers can make the right decision. Design and test Design, design for testability (DFT) and test time, budgeting considerations, marketing, quality and reliability, target throughput, training, packaging technology, circuit layout, silicon, pin out, CAD tools, designers' skills, performance degradation, computing equipment, and capital investment DFT and ATE Purchasing, depreciation and maintenance, operator and programming salaries, other labor rates, setup time, test program length, pin memory, program fault coverage, program preparation time, test and diagnosis time, test fixtures, manufacturing yield, production volume, and number of board types Field service Repair depot, logistics support, field repair, downtime, repeat visits, and design for maintainability

show abstract

“…Consider the military, with smaller volumes of higher-complexity items but an urgent requirement for maintainability. 3 Test must economically span both extremes.…”

Section: Test Costmentioning

confidence: 99%

Economics of built-in self-test

Ungar

Ambler

2001

IEEE Des. Test. Comput.

Self Cite

View full text Add to dashboard Cite

show abstract

“…How to make test trade-offs is one of the major testing cost-reduction problems. Although the testing cost-reduction problem has been an important research topic in test economics of IC manufacturers [1][2], effective methods for alternative test strategies of IC designs that lead to maximum testing cost-reduction under design-and-test environments still pose significant challenges to both researchers and practitioners [3][4].…”

Section: Introductionmentioning

confidence: 99%

An economic selecting model for DFT strategies

Lin

Ambler

23rd IEEE VLSI Test Symposium (VTS'05)

Self Cite

View full text Add to dashboard Cite

Exploiting the knowledge-based technology and multi-objective analysis, this paper presents a selecting model and its prototype implementation for design for testability (DFT) strategies. Cores to the knowledge-based selecting are decision tree-based knowledge representation models. Keys to the decision tree model are human-like decision procedures and time elimination of defining cost related equations. Test runs over a design-and-test compatible environment demonstrate both feasibility and potential effectiveness of the decision tree selecting model to support both the current and future needs of VLSI testing.

show abstract

Cost benefits for the application of COTS ATE

Cited by 2 publications

References 0 publications

Economics of built-in self-test

Economics of built-in self-test

An economic selecting model for DFT strategies

Contact Info

Product

Resources

About